PSoC™ 6 Forum Discussions

Hello,

I am trying FreeRTOS with CY8CKIT-062-BLE.

Please see the attached project.

Task A and Task B are scheduled by pressing SW2 after reset release, and are switched every 1 ms.

However, after pressing SW2, the start message is displayed and only TaskA is executed for about 9ms.

Why doesn't TaskA and TaskB switch for 9ms?

Best regards,

Yocchi

Hello,

I am working on a master thesis project where basically I need to create a stand alone datalogger. While connection to the different sensors is not an issue, I cannot find an "easy" way to save the data somewhere and read it on a PC (best would be to generate a csv file).

I am trying now to save the data on a SD card using SPI communication and FatFs. However, it seems there is no code working "out of the box" and my experience is very limited, so I ask for help to the community.

I have found the following GitHub

GitHub - hackingchips/PSoC_FatFs: Port of ELM-CHAN FatFs library to Cypress PSoc microcontrollers.

I've tried to modify the sdcard.c and main file (my files in attachment) to match PSoC 6 macros, but I always get a "sdcard not ready" error.

I have also tried to use the workaround code given in emFile component for PSoC 6 . I can read the files on the card, but the code does not include any writing capability and implement it myself is out of my league.

Can I get help from somebody? Or perhaps, does anybody already have a working code?

BTW, I am using Clicker 2 for PSoC® 6 with a microSD click.

Thanks a lot

Davide

I'm trying to run a low power application that goes into deep sleep when idle, and whenever I enable the crypto HW and then disable before entering deep sleep the current draw when in deep sleep is significantly higher (~1mA) than if I just skip the Cy_Crypto_Enable/Cy_Crypto_Disable operation all together. For this simple experiment, I am  just doing an enable and then disable during initialization before allowing the system to go into deep sleep. I'm fairly confident that the crypto server operations are completing before going into deep sleep. I'm just wondering if I'm missing anything (disabling clocks, etc) that would actually power down the crypto block to achieve the power consumption I'm expecting?

I'd like to know that Specific Absorption Rate (SAR) of  CYBLE-416045-02 since FCC Part 15 Subpart C as potable device.

How can I find the datasheet of SAR of CYBLE-416045-02?

Hi,

This question is related the question below

PSoC 6 Vbackup current

The customer is seriously trying to estimate the backup coin battery life.

And they asked us if the battery can be drained by P0 during VDDD is present.

At first from the description of 15.3 Power Supply, I thought that only when VDDD voltage goes lower than VBACKUP,  it can happen.

================

VDDBAK_CTL = 0 (Default mode): Selects VDDD when the brownout detector in the system resources is enabled and no brownout situation is detected (see the

Power Supply and Monitoring chapter on page 129 for more details). Otherwise, it selects the highest supply among VDDD and VBACKUP.

================

But seeing the diagram, I noticed the path (red line) exists, which is not controlled by the Backup Power Switch.

So I lost my confidence. It looks like if some port sync a lot of current, Vbackup can be used to help VDDD.

Question:

Is there a case when VDDD presents, but VBACKUP is also consumed?

Especially when VDDD is not lower than VBACKUP (but current may not be sufficient.)

moto

I work for a non profit organization for "Human Trafficking". I was looking at the PSoc 6 version. Or Psoc 1. I am looking for two way audio and digital communication using WiFi. I do not know the range of the WiFi on the Psoc6 version but I can always add a WiFi repeater. I will also need one port to send predefined messages. There will be an operator at the reception desk.

What would be the best choice for two way audio, at least one IO port.

Note: I have been tasked to set up the file server server, Security cameras and intrusion alarms. My plate is full. I need a SDK to get on line ASAP. Please send me an email for more details. I am handicapped and I will have at least two technicians to do the manual work. I have Orthostatic Hypo tension. I can't control my blood pressure.I will need at least 100 of these SDK boards. I do not have time to develop the board. I can do a Psoc 1 board. But I don't know what to use for audio and WiFi.

pfn2001@att.net

We're working on a project that requires 5 or 6 hardware counters. Using Count7 works well, but we only need 3 bits of those counters and we're running out of UDBs for other tasks.

So: is it possible to implement 2 3-bit counters using just one UDB? That would be quite a relief. We'd need (roughly) the following API:

- initialize and enable

- set period

- read and write current counter value

The component would have two clock inputs and two cnt[2:0] outputs. A tc output is not necessary.

Hi,

I'm digging deeper into the PSoC 6 devices. As far as I can see PSoC 63 and upwards are BLE 5.0 devices. Will they also support BLE 5.1? Is this only related to the BLE software stack or would it need a new device?

Regards