PSoC™ 6 Forum Discussions
The CY8CPROTO-063-BLE board is being used with hibernate and periodic alarms to save system power. The RTC is producing the expected alarms and the hibernate control is working properly. There is an external PMIC with an enable input to turn it on and off to generate the 3.3V input for the VDD . A supercap is attached to VBACKUP and R29 is removed on the board. When the unit is also powered from the KipProg3 adapter (via VTARG) it works as intended, hibernating and waking up periodically. However, When the KitProg3 is unpowered and the external power is only applied into the PMIC, it never gets out of hibernation.
The problem is that pin P0.5 is not being controlled by the hibernate logic as needed. The PMIC enable (active high) is pulled high by a weak pull-up resistor for when the PSoC 6 is not yet powered or not yet in control ( P0.5 assumed high impedance). When hibernate mode is started, P0.5 should be pulled low by the PmicEnableOutput and when it goes out of hibernate, it should be pulled high to turn the external PMIC on. This is not happening.
In response to the forum question "PSoC 6 PMIC Control deep sleep best practise", GaneshD_41 replied suggesting control that is built into the following code:
Cy_SysPm_SetHibWakeupSource( CY_SYSPM_HIBALARM // Wake-up source for RTC alarm
| CY_SYSPM_HIBPIN1_LOW // Wake-up source for Pin1 input low
);
Cy_SysPm_PmicUnlock(); // Unlock in case locked
//NU Cy_SysPm_PmicEnable(); // enable Pmic control
Cy_SysPm_PmicEnableOutput(); // enable P0.5 output control
Cy_SysPm_PmicLock(); // Lock again but why?
// Configure the PMIC controller output pin to be active logic low
// after the PMIC is disabled.
// Note: I do not understand the above comment
Cy_GPIO_SetDrivemode(P0_5_PORT, P0_5_PIN, CY_GPIO_DM_STRONG_IN_OFF); // What does this do?
Cy_GPIO_Clr(P0_5_PORT, P0_5_PIN); // What does this do?
if ( Cy_SysPm_PmicIsOutputEnabled() ) // It was just enabled above; so why check?
{
Cy_SysPm_PmicUnlock();
Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW); // what does this do?
}
// Prepare the device for system Hibernate
if ( Cy_SysPm_SystemEnterHibernate() != CY_SYSPM_SUCCESS )
{
/* System did not enter Hibernate mode because a registered
* Hibernate "check ready" callback returned a "not success" status
*/
printf(" Hibernate failed\r\n\n");
Cy_SysLib_Delay(1000); // wait for output
failed= 1;
}
The above code was put into the project; yet P0.5 still does not have any output; it always stays low.
Are there any suggestions as to properly controlling the P0.5 pin while going into and out of hibernation?
Show LessHello,
I am very new to the world of BTLE, but have a large background in electrochemistry. I am currently curious about trying to power the PSOC6 purely off electrochemical reactions (glucose and glucose oxidase). I wold like to measure the potetnial over a resitior, or charge pump, or anyhting that would minimize power, and simply send that raw value via bluetooth in the lowest energy consuming form possible. I apologies if this is to vauge. If there is a simpler solution then the PSOC6 (from what i hear this is a very complex chip) i am all ears!
thanks,
David Probst
Show LessHello,
I want to know the CPU current of the PSoC61 series, but the datasheet only has information about dual-core device (why?).
Please tell me the CPU current specifications for single-core products.
Regards,
Shimamura
Show LessHi:
Why the device nane , the defined symbols field of C/C++ compiler can't change synchronously When I change the devices from CY8C624ABZI-D44 to CY8C624AAZI-S2D44? It will lead to a Mistake to inclde the header file of cy8c624abzi_d44.h!!!
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In PSoC 6 MCU with BLE: CY8C63x6, CY8C63x7 Architecture TRM, Document No. 002-18176 Rev. *H, section 25.6 SCB Interrupts, it says: "Note: To avoid being triggered by events from previous transactions, whenever the firmware enables an interrupt mask register bit, it should clear the interrupt request register in advance." I'm not sure what they are referring by "interrupt request register ." Would that be INTR_M?
In my mainline code, I have
/* Unmasking only the spi done interrupt bit */
this->spi->base->INTR_M_MASK = SCB_INTR_M_SPI_DONE_Msk;
and in my ISR,
/* Mask the spi done interrupt bit */
this->base->INTR_M_MASK &= ~SCB_INTR_M_SPI_DONE_Msk;
Is the Architecture TRM saying that before I unmask the SPI Done bit in INTR_M_MASK I should clear INTR_M?
From PSoC 6 MCU: CY8C61x6, CY8C61x7 Registers TRM, Document Number: 002-23456 Rev. *C 1255, it looks like the SPI_DONE bit is RW1C. Should I do something like
/* Unmasking only the spi done interrupt bit */
this->spi->base->INTR_M = SCB_INTR_M_SPI_DONE_Msk; // Clear request register; RW1C
this->spi->base->INTR_M_MASK = SCB_INTR_M_SPI_DONE_Msk;
That doesn't seem quite right, because I'm only clearing one bit, but the TRM says I should "clear the interrupt request register."
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Hello
Questions related to this thread.
Customer using CYBLE-416045-02.
Files built using PSoC Creator vary in size depending on the PC on which they are created.
(Version4.3)
As a verification, I built a sample program of "BLE_Alert_Notification" and compared customers HEX, but the size was different.
When I checked it with software that compares HEX files, I found data that existed in only one of them.
What is the cause of this?
Best Regards
Hayato
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https://www.cypress.com/products/psoc-6-microcontrollers-32-bit-arm-cortex-m4m0
No devices appear on PSoC 64 product selector.
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Hello, I need to create a simple LCD display like the one in the photo, but with the PSOC 6.
But I couldn't quite understand the LCD interface of PSOC 6. Does anyone have an example of an LCD display to simply show a string like "Hello World!"? If so, could you provide an example project?
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