PSoC™ 6 Forum Discussions

Can anyone tell me the execution context of the callback function passed to Cy_BLE_Start()? Is it the same execution context as Cy_BLE_ProcessEvents() or is it executing in an interrupt?

I debugged to the first line in the callback function and it shows a continuous call stack through Cy_BLE_ProcessEvents() right up to main() but I'm not 100% sure that it's accurate evidence of the same execution context.

I need to know because of my application will access data blocks in the callback function and the main loop so I need to protect the data block integrity if the execution contexts are different.

Thanks - JJS

Hello, I am doing a project with PSoC 63 BLE pioneer kit and WS2812b LED matrix. And I found alan has posted a tutorial about how to control WS2812 with PSoC 6 DMA.  And I downloaded the code and running the program on my own kit. But it didn't work. I use the oscilloscope to measure the signal from the output port(p0.3), there is no signal.  can someone tell me how to solve this problem? I am now a beginner of PSoC and stuff with hardware, I really don't know how to solve it. I noticed that the PSoC 6 is a 3.3v microcontroller and the WS2812 is a 5V component. Do I need to add a level shifter between them?

The following is the blog and code I use and my hardware connection. Blog: https://iotexpert.com/psoc-6-dma-ws2812-leds/

Hello,

i'm trying to develop an Ionic application.
One of the functionality is the Firmware Update.
Do you know if anyone already develop an application like me ?

I have some problems , i would like talk about it with someone ...

Kévin. 

Hi Cypress,

I recently upgrade to the Creator 4.4 and PDL 3.1.3, which are all the latest, see below.

Then I am creating the ADC block for my sensors, which is using the internal multiple channels inside the ADC.

I noticed the other post that a PORT 10 must be used in order to use the internal MUX, which i did.

Unfortunately, I still have multiple errors about this ADC setup. 

Here is the Analog tab:

Here is the schematic page:

What is going wrong with the library or the setup?

Please advise. Thanks!

Gilbert

Hi everybody. Hi have made my own board with CYBLE-416045-02. I have put on V_Backup pin a 3V battery. When I remove VDD (in the schematic VCC_3.3_CYBLE) RTC resets to the last saved datetime. Can You help me? Thanks. In the follow I have attached the piece schematic and the init code of rtc

void init_rtc(void){
cyhal_rtc_init(&my_rtc);
}

I'm currently finalizing a hardware design using the PScC6 Creator module and want to know if any of the available IO pins can be used to wake the PSoC6 out of deep sleep or hibernate mode? Currently, I have a push-button connected to pin P9.2, which will ground it when pressed. My idea is to include a denounce circuit inside the PSoC6 (based on this app note here) and wake it from the lowest possible sleep mode. Are there any other things I need to consider for this use case?

Thanks!

Jason O

Hello all,

I am currently using a psoc CY8C6347BZI-BLD53 to do some very high speed SPI transfers at 25MHz and have come across some interesting behavior of the SPI FIFO. 

Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8. Upon further investigation with an oscilloscope there was some delay between transfers  (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.

The delay between each message becomes one clock cycle consistently when using Cy_SCB_WriteTxFifo() even while writing to the FIFO which solves my timing critical problem. However, I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38) . I found that if I add a delay of ~20 cycles after each call of Cy_SCB_WriteTxFifo() the right number of data (54) can be seen transferring on the oscilloscope before the next interrupt occurs.

I am reaching out for some help with trying to eliminate the added delay cycles after each Cy_SCB_WriteTxFifo, or at least to understand the root cause of why it work when they're there. I have looked into the TRM for the architecture, but they do not go into detail about FIFO operation. I don't have a usb right now so I can't post images from my oscilloscope but if you need them to understand I should have one by this Monday.

Your help is greatly appreciated!