PSoC 6 MCU

I have a Psoc 6 I2C master.  The desired frequency is 100kHz.  The configuration window says the actual frequency is 96kHz, SCB clock 1548kHz.  With a scope, I'm measuring 49kHz on SCL.

The symptom is occasionally, there is an unexpected extra byte of data received from the slave.  Using a 3rd party I2C tool, the data received is as expected.

What might be wrong? 

Build environment: PSoC Creator 4.4, Windoze 7, PDL 3.1.3
Target Hardware: CY8PROTO-063-BLE

I am working on a project that started out as the PSoC 6 BLE Battery Service demo. I moved everything related to BLE to the M0P CPU, because that is how my system will be structured - I have lots of other things for the M4 to do, including making use of the FPU.

I was able to get this to build and run without any particular issues. There was nothing running on the M4 except the default code to put it to sleep.

I have now started to implement the M4 code, which includes some hardware that will be dedicated to the M4. But so far, no actual code that does anything. There is some shared source code, but it is not called on the M4.. yet.

Now the linker step of the build fails, indicating that something went wrong during the process of merging the code for the two CPUs.

There are no errors reported up to this point:
\Debug\cy_ble_event_handler.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ancs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ans.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_aios.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bas.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bcs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bms.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cgms.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cscs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_custom.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_dis.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ess.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_gls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hids.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hrs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ias.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ips.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_lls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_lns.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ndcs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_plxs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_pass.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_rscs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_rtus.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_scps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_tps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_uds.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_wpts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_wss.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_clk.o .\CortexM0p\ARM_GCC_541\Debug\timer.o .\CortexM0p\ARM_GCC_541\Debug\I2C.o .\CortexM0p\ARM_GCC_541\Debug\ADC.o .\CortexM0p\ARM_GCC_541\Debug\ADC_INT.o .\CortexM0p\ARM_GCC_541\Debug\ADC_INIT.o .\CortexM0p\ARM_GCC_541\Debug\ADC_PM.o .\CortexM0p\ARM_GCC_541\Debug\SPI.o -mcpu=cortex-m0plus -mthumb -L Generated_Source\PSoC6 -Wl,-Map,.\CortexM0p\ARM_GCC_541\Debug/PSoC6_BLE_UI.map -T cy8c6xx7_cm0plus.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -Og -ffat-lto-objects -Wl,--end-group
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__StackTop':
(.stack+0x1000): multiple definition of `__StackTop'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:(.stack+0x1000): first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__StackLimit':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__StackLimit'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__HeapBase':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__HeapBase'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__HeapLimit':
(.heap+0x400): multiple definition of `__HeapLimit'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:(.heap+0x400): first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__Vectors':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__Vectors'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
ERROR: Warning: size of symbol `__Vectors' changed from 192 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o to 652 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__ramVectors':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__ramVectors'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
ERROR: Warning: size of symbol `__ramVectors' changed from 192 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o to 652 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o
.\CortexM0p\ARM_GCC_541\Debug\main_cm4.o: In function `main':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/main_cm4.c:55: multiple definition of `main'
.\CortexM0p\ARM_GCC_541\Debug\main_cm0p.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/main_cm0p.c:56: first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o: In function `SystemCoreClockUpdate':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/system_psoc6_cm4.c:290: multiple definition of `SystemCoreClockUpdate'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/system_psoc6_cm0plus.c:295: first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o: In function `SystemInit':
system_psoc6_cm4.c:(.text.SystemInit+0x0): multiple definition of `SystemInit'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:system_psoc6_cm0plus.c:(.text.SystemInit+0x0): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x1c): multiple definition of `cy_delay32kMs'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x1c): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x14): multiple definition of `cy_delayFreqMhz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x14): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x18): multiple definition of `cy_delayFreqKhz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x18): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x10): multiple definition of `cy_delayFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x10): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x0): multiple definition of `cy_BleEcoClockFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x0): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x8): multiple definition of `cy_PeriClkFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x8): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x4): multiple definition of `cy_Hfclk0FreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x4): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0xc): multiple definition of `SystemCoreClock'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0xc): first defined here
collect2.exe: error: ld returned 1 exit status
The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
--------------- Rebuild Failed: 04/16/2021 10:56:00 ---------------

What happened here? How do I fix this?

Hi,

I had to enable the continuous scanning myself in HAL library to get the ADC running continuously.

I have modified the library mtb_shared\mtb-hal-cat1\latest-v1.X\COMPONENT_CM4\source\cyhal_adc.c

in function cy_rslt_t cyhal_adc_configure(cyhal_adc_t *obj, const cyhal_adc_config_t *config)

Line 1103:

if(config->continuous_scanning)
{
obj->continuous_scanning = true;
obj->conversion_complete = false;
Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_CONTINUOUS);
}

Before it was like  shown below:

Line 1103:

if(obj->continuous_scanning)
{
obj->conversion_complete = false;
Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_CONTINUOUS);
}

BR,

Gintaras

Why  the I2C slave interrupt sources must be enable for the Psoc6 SCB master I2C mode read or write operation?Show as the flow pictures:

 Which interrupt event will be happened for the  every step of  i2c master operation?

I have a pin set to high impedance digital and an external pull up resistor of 10k ohm to 3.3V. For some reason the pin stays at 2.35V instead of going to 3.3V.

It almost seems like the pin has some internal pull down that I am fighting.

I am using chip CY8C6347LQI-BLD52, pin P7.2

Any ideas why it isn’t going to 3.3V?

I'm just starting to look at PSoC 6 after working with 4 for quite a while, and I can't get past this first issue.

There is another post about this, along with a comment saying "we don't have this issue, it's likely to do with the pin configuration."

So I've created a new empty project in PSoC Creator, for a CY8C6247BZI-D54 ... I've put a single output pin on the schematic, and selected "Single-Sync" ... I've done nothing else and I get that warning.

I've experimented with different drive settings etc, but I can't get it to go away.

Similarly if I change it to an input pin (with hardware connection, and attach it to something like a status register) ... it's fine without sync, but with single or double-sync I get the same warning (well, InSyncNeeded.)

So I don't understand how everyone else isn't seeing this?

The family datasheets for the 4200L and the 62 family both contain the same section detailing the sync capability (PA Data Input Logic/PA Data Output Logic) ... so it's not a capability problem??

What am I missing?