PSoC™ 6 Forum Discussions
Hello.
I'm developing a mobile PSoC6 (CY8C6347FMI-BUD53) measurement system with BLE communication on Modus Toolbox (Version: 2.2.0 Build ID: 2181).
I had a trouble when I was building a custom BSP.
I made a new project from "New Application" in Quick Panel. I selected the "PSoC6-Generic" in Project Creator(ver.1.2). Then I made a build target from the left-click submenu on the project name.
I was able to build the target about a week ago.
but I couldn't build and the error message below was shown in the console of the Modus Toolbox.
"Could not find schema to validate (Workspace directory)/mtb_shared/mtb-pdl-cat1/latest-v2.X/personalities/peripheral/sar-4.0.cypersonality against. Check the xmlns version against the ../personalities/version.xml file contents."
Maybe it will be the error about personality file.
I don't know why it suddenly happened.
Is there somebody who encountered same trouble, or know how to fix the problem?
Regards,
Keiichi
Show LessTLDR:
- How do I get ITM_SendChar() output working in a ModusToolbox project, using the VSCode IDE?
- Does the PSoC6 implement a standard Cortex-M4 "TPI/TPIU" or custom "TPIU lite"?
- Where can I find the documentation for the correct subsystem?
- What core hardware configuration is needed to enable SWO output?
---
I am attempting to get SWO debug output from the Cortex-M4 core via the SWD interface with the following environment.
- Toolset: ModusToolbox, gcc, openocd
- IDE: VSCode
- Debugging Extension: cortex-debug
- Programmer: Cypress MiniProg4, 10-pin connection
- Target MCU: PSoC62, CY8C624AAZI-S2D44
When adding a swoConfig section to the "Launch PSoC4 CM4 (KitProg3_MiniProg4)" configuration in .vsocde/launch.json
and connect the debugger, the cortex-debug plugin complains with
'Failed to launch GDB: Cannot access memory at address 0xe0040304 (from interpreter-exec console "BaseSWOSetup 49")'
This corresponds to the script the cortex-debug plugin is trying to run here.
The address 0xe0040304 corresponds to the TPI->FFCR register, as is defined by lib/psoc6pdl/cmsis/include/core_cm4.h.
(Note: It would appear that documentation/code tends to dither between using the terms TPI and TPIU)
In a working debug session (without swoConfig), a dump of the entire TPI memory region (0xe0040000 - 0xe004FFFF) only returns 0x00 data. At the very least, I would expect some non-zero data for the TPI->DEVID and TPI->DEVTYPE registers. Every time a dump of that memory region is performed, the 'Adapter Output' window also reports "Error: Failed to read memory at 0xe0040004" - and only that address in the region.
New window opens showing 64kB of 0x00 data, starting at 0xe0040000, as well as an error in the Adapter output:
[ 91%] [############################# ] [ Programming ]
[ 94%] [############################## ] [ Programming ]
[ 97%] [############################### ] [ Programming ]
[100%] [################################] [ Programming ]
wrote 2097152 bytes from file C:/git/gen3-firmware/build/gen3-main/Debug/GEN3_PSOC6.gen3_bundle in 30.425264s (67.312 KiB/s)
** Programming Finished **
Info : psoc6.cpu.cm4: external reset detected
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x0802a210 psp: 0x0804ab00
Info : psoc6.cpu.cm4: bkpt @0x08018341, issuing SYSRESETREQ
Info : psoc6.cpu.cm4: external reset detected
Info : psoc6.cpu.cm4: external reset detected
target halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x08018340 msp: 0x080ff000
Info : psoc6.cpu.cm0: external reset detected
Info : SWD DPIDR 0x6ba02477
Error: Failed to read memory at 0xe0040004
Info : SWD DPIDR 0x6ba02477
Error: Failed to read memory at 0xe0040004
There are a small number of threads in this forum that deal with the same problem of trying to get SWO debug output to work:
- Is the SWO Pin at PSOC63 working? (Solution marked is about finding the Special Function Register file for Keil, and is unrelated to the initial problem)
- PSOC6 Serial Wire Viewer(Is is unclear from the comments what the solution actually was, and starts with a project created by PSoC Creator, rather than ModusToolbox)
This post in the first thread points out that a project created in PSoC Creator generates code for the PSOC6 CM4 with support for a 'TPIU lite' at address 0xe008e0000. I created a 'Hello World' application in PSoC Creator and confirmed that there is
- Definition of TPI registers at 0xe004000 in Generated_Source/PSoC6/pdl/cmsis/include/core_cm4.h
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - Definition of TPIU registers at 0xe008e000 in Generated_Source/PSoC6/cydevice_trm.h
#define CYDEV_CM4_TPIU_BASE 0xe008e000u
#define CYDEV_CM4_TPIU_SIZE 0x00001000u
The source code generated/imported by ModusToolbox (2.1) only includes the cmsis header file. I have further confirmed that the mtb-pdl-cat1 library, which would be used by a ModusToolbox 2.2 project, only has the TPI defines in the cmsis headers.
I have scoured the Cypress PSoC62 documentation - data sheet, technical reference manual, and register reference manual
The best level of documentation I have found for this subsystem so far is the following from the technical reference manual:
'The TPIU drives the external pins of a trace port (through
IOSS interface), so that the trace can be captured by an
external trace port analyzer (TPA). For more details, refer to
the Arm Debug Interface Architecture Specification ADIv5.0
to ADIv5.2.'
The Arm Debug Interface Architecture Specification ADIv5.0 to ADVIv5.2, does not appear to document a TPIU.
The Cortex-M4 Technical Reference Manual does have a section on the TPIU programmers model, however based on earlier testing, and the initial error code mentioned, this does not appear to line up with TPIU implementation on the PSoC6.
The About the Cortex-M4 TPIU section of the Cortex-M4 Technical Reference Manual does have this line:
'Your implementation can replace the Cortex-M4 TPIU with other CoreSight components if your implementation requires the additional features of the CoreSight TPIU.'
At the end of all of this, I am no closer to understanding what the applicable documentation is for the PSoC6's Debug/ITM/TPI hardware.
---
- Does the PSoC6 have a standard Cortex-M4 TPI unit?
- If not, what does it have - and what is the appropriate reference documentation?
- Is there some other PSoC6 register configuration, for example in the CPUSS block, that is needed before the TPI can be accessed?
- Is it a bug that CYDEV_CM4_TPIU_BASE was defined in PSoC Creator, or that it is missing when using ModusToolbox?
Apologies for the length of this post, and thanks in advance.
Show LessBuild environment: PSoC Creator 4.4, Windoze 7, PDL 3.1.3
Target Hardware: CY8PROTO-063-BLE
I am working on a project that started out as the PSoC 6 BLE Battery Service demo. I moved everything related to BLE to the M0P CPU, because that is how my system will be structured - I have lots of other things for the M4 to do, including making use of the FPU.
I was able to get this to build and run without any particular issues. There was nothing running on the M4 except the default code to put it to sleep.
I have now started to implement the M4 code, which includes some hardware that will be dedicated to the M4. But so far, no actual code that does anything. There is some shared source code, but it is not called on the M4.. yet.
Now the linker step of the build fails, indicating that something went wrong during the process of merging the code for the two CPUs.
There are no errors reported up to this point:
\Debug\cy_ble_event_handler.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ancs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ans.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_aios.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bas.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bcs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bms.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_bts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cgms.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cscs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_cts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_custom.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_dis.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ess.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_gls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hids.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hrs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_hts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ias.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ips.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_lls.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_lns.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_ndcs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_plxs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_pass.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_rscs.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_rtus.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_scps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_tps.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_uds.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_wpts.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_wss.o .\CortexM0p\ARM_GCC_541\Debug\cy_ble_clk.o .\CortexM0p\ARM_GCC_541\Debug\timer.o .\CortexM0p\ARM_GCC_541\Debug\I2C.o .\CortexM0p\ARM_GCC_541\Debug\ADC.o .\CortexM0p\ARM_GCC_541\Debug\ADC_INT.o .\CortexM0p\ARM_GCC_541\Debug\ADC_INIT.o .\CortexM0p\ARM_GCC_541\Debug\ADC_PM.o .\CortexM0p\ARM_GCC_541\Debug\SPI.o -mcpu=cortex-m0plus -mthumb -L Generated_Source\PSoC6 -Wl,-Map,.\CortexM0p\ARM_GCC_541\Debug/PSoC6_BLE_UI.map -T cy8c6xx7_cm0plus.ld -specs=nano.specs -Wl,--gc-sections -g -ffunction-sections -Og -ffat-lto-objects -Wl,--end-group
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__StackTop':
(.stack+0x1000): multiple definition of `__StackTop'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:(.stack+0x1000): first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__StackLimit':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__StackLimit'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__HeapBase':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__HeapBase'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__HeapLimit':
(.heap+0x400): multiple definition of `__HeapLimit'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:(.heap+0x400): first defined here
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__Vectors':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__Vectors'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
ERROR: Warning: size of symbol `__Vectors' changed from 192 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o to 652 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o: In function `__ramVectors':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm4.S:273: multiple definition of `__ramVectors'
.\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/gcc/startup_psoc6_01_cm0plus.S:157: first defined here
ERROR: Warning: size of symbol `__ramVectors' changed from 192 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm0plus.o to 652 in .\CortexM0p\ARM_GCC_541\Debug\startup_psoc6_01_cm4.o
.\CortexM0p\ARM_GCC_541\Debug\main_cm4.o: In function `main':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/main_cm4.c:55: multiple definition of `main'
.\CortexM0p\ARM_GCC_541\Debug\main_cm0p.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/main_cm0p.c:56: first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o: In function `SystemCoreClockUpdate':
C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/system_psoc6_cm4.c:290: multiple definition of `SystemCoreClockUpdate'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:C:\projects\ib\Roadkill\05_PSoC6\PSoC6_BLE_UI\PSoC6_BLE_UI.cydsn/system_psoc6_cm0plus.c:295: first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o: In function `SystemInit':
system_psoc6_cm4.c:(.text.SystemInit+0x0): multiple definition of `SystemInit'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:system_psoc6_cm0plus.c:(.text.SystemInit+0x0): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x1c): multiple definition of `cy_delay32kMs'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x1c): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x14): multiple definition of `cy_delayFreqMhz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x14): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x18): multiple definition of `cy_delayFreqKhz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x18): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x10): multiple definition of `cy_delayFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x10): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x0): multiple definition of `cy_BleEcoClockFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x0): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x8): multiple definition of `cy_PeriClkFreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x8): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0x4): multiple definition of `cy_Hfclk0FreqHz'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0x4): first defined here
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm4.o:(.data+0xc): multiple definition of `SystemCoreClock'
.\CortexM0p\ARM_GCC_541\Debug\system_psoc6_cm0plus.o:(.data+0xc): first defined here
collect2.exe: error: ld returned 1 exit status
The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
--------------- Rebuild Failed: 04/16/2021 10:56:00 ---------------
What happened here? How do I fix this?
Show LessBought a new board : CY8CPROTO-062-4343W and I tried blinky demo and it was OK.
After using AtmosphereIot agent, I'm no more able to reprogram the board. I get this message :
Info : kitprog3: acquiring the device (mode: reset)...
Error: kitprog3: failed to acquire the device
Info : clock speed 2000 kHz
Error: DAP 'psoc6.cpu' initialization failed (check connection, power, transport, DAP is enabled etc.)
** OpenOCD init failed **
shutdown command invoked
** Program operation failed **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Error executing event reset-deassert-post on target psoc6.cpu.cm0:
C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg:108: Error:
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279
in procedure 'mxs40_reset_deassert_post' called at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 131
at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg", line 108
Error executing event reset-deassert-post on target psoc6.cpu.cm4:
C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg:108: Error:
in procedure 'ocd_process_reset'
in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279
in procedure 'mxs40_reset_deassert_post' called at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 166
at file "C:/Infineon/Tools/ModusToolbox/tools_2.3/openocd/bin/../scripts/target/mxs40/mxs40_common.cfg", line 108
Info : psoc6.dap: powering down debug domain...
Warn : Failed to power down Debug Domains
Any Help ^
Thanks
Show LessHi,
The ADC_basic example which is present under PSoC BSPs->CY8CKIT-062S4 (device CY8C6244LQI-S4D92) is without modustoolbox GUI setting. In this example, the adc setting is done using firmware.
Could you provide a simple ADC example with modustoolbox GUI setting of ADC?
Thanks
Show LessI am using a Cy8cproto-063-BLE board to program other psoc 1 and psoc 4 target boards. The setup works fine, but after a while the cy8proto-063-BLE breaks. The MCU does not react to anything and is sometimes shorted fromt VCC to GND.
When I measure my circuitry, I don't measure any signals that transcend the Absolut Maximum Ratings. The 3.3V VCC is provided by a Meanwell IRM-03-3.3.
I think the problem might have something to do with ESD. In the "PSoC 6 BLE Prototyping Board Guide" I found This:
Is there anybody who has any tips for me?
Show LessHello,
I have a server which has more than one Miniprog3 connected to it and multiple users use this server to connect to their own PSoC6 boards through separate instances of ModusToolBos IDE.
I tried modifying '/openocd/scripts/interface/kitprog3.cfg' to include 'kitprog_serial <miniprog4 serial number>' assuming it would ensure the MTB instances would connect to the appropriate Miniprog4 instances, but it would alsways fail to connect. Is this the right way yo achieve this? I have taken the serial number of the Miniprog4 from it's label. Eg: 1939CN00107
In short, I would like ModusToolBox IDE to choose between multiple Miniprog4 connected in the same system to program/debug.
thanks,
Suresh
Show LessHello, everybody.
I'm developing a mobile PSoC6 (CY8C6347FMI-BUD53) measurement system with BLE communication on Modus Toolbox (Version: 2.2.0 Build ID: 2181).
I can monitor all the BLE events for debug by sending the message to the terminal PC through UART. My PSoC6 system have Peripheral and Observer role and have two characteristic, 'write' characteristic and 'read/notify' characteristic.
Now I have a trouble in BLE communication.
When I wrote data to the 'write' characteristic from central device (android smartphone), CY_BLE_EVT_GATTS_WRITE_REQ event arose twice every time. Contents of the event parameter variable in the both events were completely same. Other events arose only once every time.
The firmware on this system was transported from the firmware which was developed for PSoC4 on PSoC Creator, and the system worked well, of course without duplicated WRITE_REQ events.
I temporarily revise the firmware to ignore the second WRITE_REQ event, and it looks working well.
But I want to know how it arise fundamentally and correct the firmware not to arise duplicated event perfectly.
Please teach me something if you have a hint or know how to solve the problem.
Thank you for reading.
Keiichi
Show LessI have a Psoc 6 I2C master. The desired frequency is 100kHz. The configuration window says the actual frequency is 96kHz, SCB clock 1548kHz. With a scope, I'm measuring 49kHz on SCL.
The symptom is occasionally, there is an unexpected extra byte of data received from the slave. Using a 3rd party I2C tool, the data received is as expected.
What might be wrong?
Show Less