PSoC™ 6 Forum Discussions

Sorry to disturb everyone.

I encountered a difficult problem.

In Psoc6, how to configure the pins in port9 as SAR AD pins without generating DSI interrupts. What I configured will always generate DSI interrupts, so the program enters Cy_HALT() .

Thank you very much for your help

Hi everyone, excuse me.

I have an urgent question.

After Modus is compiled, the RAM usage size will be displayed. I found that the same code, on modus, the heap usage is very large, but it is very small on other compilers, so that my SRAM on MODus is about to exceed.

Total Internal SRAM (Available) 292864
Total Internal SRAM (Utilized with heap) 279920

thanks for your help

Hello,

I am using a CY8C6347BZI-BLD53 and ble connections are working well with iOS and Android clients. However, establishing a BLE connection with windows is unreliable; sometimes it works, some times it doesn't. I've used a protocol analyzer to capture the BLE traffic while establishing a connection with windows and have found that when a connection doesn't work, the PSoC6 doesn't acknowledge the LL_FEATURE_REQ sent by the windows radio and the windows radio retransmits that packet until the connection times out. What could cause this behavior?

I've attached a couple of screenshots of the packet trace showing the issue. Frame 8,308 is the connection indication and it is immediately followed by the LL feature request on frame 8,309. Frame 8310 doesn't acknowledge frame 8,309 and then it gets retransmitted a lot of times, never being acknowledged by the PSoC6. I'm happy to upload the full packet trace to a non-public forum, it contains both successful and unsuccessful connections.

Thanks,

Theo

Hi,

I am using Toshiba NAND flash with CY8CKIT-062S2-43012. I am using this flash for OTA using HTTP with the sample application. The bin file is downloaded to NAND flash. The download is successful. After the download the board reboots and reads magic number, swap_type, image_ok flag and copy_done flag. The function boot_write_copy_done() is supposed to write the copy_done flag. Can you tell me where is it getting called in the flow?

Reboot happens after OTA and then it results in following error:

[ERR] ********No bootable image in slot

Please find the attached screen shot

Should I update any variable in the code, so that the bootloader should look for image in the Toshiba NAND flash instead of the default QSPI NOR flash?

Also please tell me the steps carried out during validation of image in secondary slot. Do you have any documents or links regarding this?

Any information will be of great help.

Thanks,

Binsy M S

Hi,

Currently I am testing aws_demos example in ModusToolbox2.2.
When I was using CY8CPROTO-062-4343W Rev06(IC marked with A33), I am able to reprogram and switch between different projects.

But when I changed to CY8CPROTO-062-4343W Rev08(IC marked with B33), I only programmed once and it seems the program had not been properly flashed into the board. The debug port was totally shut down and I cannot reprogram any more.

Even when I pressed SW3 to switch mode, also can not do it. It will go back to "KitProg3 CMSIS-DAP" in device manager. Please refer to the attached picture. I already killed several Rev08 boards when I was trying to program aws_demos into these Rev08 Boards.

Below is the log from Cypress Programmer when I'm trying to connect.

Please help to analyze and debug. Thank you very much. 

I am using the CY8CKIT-062-Wifi-BT Pioneer kit which comes with the CCG3 Type-C controller. By default, the Type-C connection acts as a PD power source.

I would like to know how to control CCG3 controller using Modustoolbox. To be more specific, I would like to have some reference source code that is able to control the CCG3 as and when it will supply power to another PD device.

Can you show me any reference code, library or HAL that communicate with the CCG3 controller in Modustoolbox environment?

Thanks.

Hi,

One of my customer wants to measure time between external IRQ signal,

which is supposed to be about 1ms.

So I tried with the following schematic using CY8CKIT-062-BLE.

Note: Counter_2 is used to generate dummy IRQ signal generator.

And Tera Term output seems to be OK,

Note : I'm changing the interval by 1 in the firmware loop.

But the customer is anxious if triggering both reload and capture with same edge could cause wrong sequence,

for example, if there is/are chance that the captured value is the reload(ed) value (aka 0).

IMHO, if TCPWM was designed in usual sync manner, 

the following two will take place at the same time,

so captured value won't be overwritten with the reload value.

(1) Counter Value -> Capture Value

(2) 0 -> Counter Value

Question: Is my assumption correct?

Or is/are there something I need to be aware of to do this measurement?

My test project is attached.

moto

Hello everyone,

I'm working on a project that involves a legacy ASIC that requires an external DMA controller with full DREQ/DACK mechanism. Unfortunately, non of the microcontrollers available today provide that type of DMA. Well, I'm talking here about a fully fledged DMA controller similar in signaling and behavior to that of Intel's 8237. Bitbanging, playing with address bits/signals of FMC or any workaround is not acceptable for me.

Recently, I got some suggestions to implement it using a CPLD or FPGA, but I've never used one in any of my designs. Someone also referred me to PSoC series, but not sure whether I can achieve what I want using the Logic Array embedded in that SoC.

Any feedback is highly appreciated!

Zaher

I have a problem with saving bonding data. When I bond with a peer device I get the CY_BLE_EVT_PENDING_FLASH_WRITE event. Then I try to save the data in Flash using the Cy_BLE_StoreBondingData API. Unfortunately, every time I call this function I have a hard-fault (especially due to the call of Cy_BLE_StoreStackData) ... I can't understand what the problem could be. Has anyone had this problem?