PSoC™ 6 Forum Discussions

Hello All,

I am trying to program a PSOC6 MCU board (CY8CPROTO-064S1-SB). I am able to successfully compile the software and start the flashing process.

However, the board shuts down after that. The terminal prints a message that there is an error during bootloader flow (image attached).

I get a warning message during the flash process that the board is pre-production version and the current software is incompatible (image attached).

Can someone please help me with this problem? Is there any work-around that I can use to successfully program the board?

ModusToolbox version - 2.3.1

Cysecuretools version - 3.1.0

I got a warning message to upgrade the firmware version during the flashing process, which I did from 1.27.707 to 2.21.1005. 

/*************************CONSOLE LOG************************************/

Open On-Chip Debugger 0.10.0+dev-4.2.0.1430 (2021-03-05-08:22)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
** Main Flash size limited to 0xD0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm4_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable
Info : Using CMSIS loader 'CY8C6xxx_SMIF_S25Hx512T' for bank 'psoc64_smif_cm4' (footprint 11612 bytes)
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Warn : SFlash programming allowed for regions: USER, TOC, KEY
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.21.1005
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 3.315 V
Info : kitprog3: acquiring the device (mode: reset)...
Info : clock speed 2000 kHz
Info : SWD DPIDR 0x6ba02477
***************************************
** Use overriden Main Flash size, kb: 832
** Silicon: 0xE262, Family: 0x100, Rev.: 0x24 (B3)
** Detected Device: CYB06447BZI-D54
** Flash Boot version: 4.0.0.9
Warn: Pre-production version of device is detected which is incompatible with this software
Warn: Please contact Cypress for new production parts
***************************************
Info : starting gdb server for psoc64.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Info : kitprog3: acquiring the device (mode: reset)...
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Info : Waiting up to 15.0 sec for the handshake from the target...
Warn : No handshake from the target, continuing anyway
Info : psoc64.cpu.cm4: external reset detected
psoc64.cpu.cm4 halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x1600400c msp: 00000000
** Programming Started **
auto erase enabled
Info : Padding image section 0 at 0x1001ba6e with 402 bytes (bank write end alignment)

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wrote 113664 bytes from file C:/../ModusPatch1/Hello_World/build/CY8CPROTO-064S1-SB/Debug/mtb-example-psoc6-hello-world.hex in 6.364500s (17.440 KiB/s)
** Programming Finished **
** Program operation completed successfully **
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : Deferring arp_examine of psoc64.cpu.cm4
Info : Use arp_examine command to examine it manually!
Info : Waiting up to 15.0 sec for the bootloader to open AP #2...
Warn : psoc64.cpu.cm4: external resume detected
shutdown command invoked
Info : psoc64.dap: powering down debug domain...

/**********************************************************************************/

(Link to earlier issue - Solved: Re: Open OCD SWD/JTAG error for CY8CPROTO-064S1-SB... - Cypress Developer Community)

@Rakshith 

Sincerely,

Aditi Prakash

Hi.

I am an engineer in Seoul, South Korea.

I got an PSoC6 Wifi BT Pioneer Kit with the TFT LCD 2.4 inch.

I am trying to work to show the sypress log  using the example source code of the CE225248_DisplayBuffer.

But I cannot.

Would you give me the information for this?

also can you give me the source of the sypress log showing in the TFT LCD?

I use the PSoC creater 4.4 version.

thanks

My E-mail : yugh@techrein.com

Hi,

I am going through the available documentation for two microcontrollers CY8C614ABZI-S2F04 and CY8C614ABZI-S2F44 and have a few concerns.

1 – We don’t see any development kits available on the Cypress website. This is an important factor to plan our development work on these MCUs. Are there any closest options to consider?

2 – These MCUs are dual-core, 2MB core is Cortex-M4 while the second core is Cortex-M0+. As per documentation second core is Cortex M0+ and is reserved for system functions. It is not available for applications. I need to know if I can completely disable the second core or not due to the power save requirements. Apparently, I have to run both cores which will double the MCU power consumption. 

3 – The PSoC Creator v4.4 which is a configurator tool like SiLabs Simplicity Studio doesn’t include 2 MB parts. I need to know if there is an updated version available from Cypress that includes these two variants CY8C614ABZI-S2F04, CY8C614ABZI-S2F44

Thanks

Dani

Hi guys,

I am using PSoC 6 PLE Pioneer board.

I have stdio redirected appropriately for debugging with an external terminal using printf and getchar

Everything has been working perfectly until the following problems appeared from nowhere and are persistent:

• printf will not output anything to the serial line.
• getchar blocks (even when the receive fifo says it is not empty and having disabled STDIN input buffering).

I thought it would be easy to debug this but I have been at it for considerably longer than I expected.

I wonder if someone could point me into an area to look at?

Many thanks.

Before connecting the interrupt pin of the sensor to the MCU, it is confirmed that the interrupt pulse is normally output from the sensor.
When connected to the GPIO input of MCU's P12[0] and A6 pins, an unintended pulse is generated and the interrupt cannot be read normally.
SPI_miso : P10[1] / Pin A11
SPI_mosi : P10[0] / Pin C12
SPI_sclk : P10[2] / Pin B11
SPI_ss0 : P10[3] / Pin C11
UART_1_rx : P5[0] / Pin N7
UART_1_tx : P5[1] / Pin L8
interrupt Pin_1 : P12[0] / Pin A6

Hi there:

Now I am using  following device and IDE to develop my BLE application with uart DFU and EEPROM usage

IDE: Psoc creator 4.4

PDL : 3.1.3

MCU : cyble-416045-02 

I want to scan advertise data on channel 37 only,

so I refered to this link and KBA218992 and try to config register "CYREG_BLE_BLELL_SCAN_CONFIG" in "cy_ble_evt_stack_on" event.

my code is list below(executed in CM4):

#define CYREG_BLE_BLELL_SCAN_CONFIG_USER (*(uint32*) CYREG_BLE_BLELL_SCAN_CONFIG)

void CentralEventHandler(uint32 event, void *eventParam)
{

     switch (event) {
     case CY_BLE_EVT_STACK_ON:
           CYREG_BLE_BLELL_SCAN_CONFIG_USER=CYREG_BLE_BLELL_SCAN_CONFIG_USER & 0xFFFF2FFF;
          break;

     ...other code

     }

}

but when I run my program to this line, MCU will get into "Cy_SysLib_ProcessingFault" function in "cy_syslib.c".

the most bothering thing is that ,

when I try to read the value  by "CY_GET_REG32(CYREG_BLE_BLELL_SCAN_CONFIG)" ,

the MCU also step into "Cy_SysLib_ProcessingFault"

the address of CYREG_BLE_BLELL_SCAN_CONFIG is defined in "cy_device_trm.h" with value "0x403c11d8u"

I also noticed that when I try to peer the memory value through memory window in debug mode，

the window will not show the value after BLE_BASE

(here we can see the ble_base address is 0x403c0000，and the memory window shows "## ## ## ##" after the that!

I wonder if there are some constrains or condition to fulfill before access BLE related register? 

Can anyone give me some hint or suggestion? 

Anyway,thanks for your reading!

Hi,

Do you know how to assign the (psoc63 68-pin) i2s pin output?