PSoC™ 6 Forum Discussions

I managed to have two Apps (each with 2 cores) in the Psoc6 flash memory, How can I start the second App from the first one (I'm trying from the main() of the M0+)?

the first App start at 0x10000000

the second start at 0x100f0000

I tried SwitchToApp(0x08002000, 0x100f0000);  from the cy_dfu.c but it triggers a HardFault

static void SwitchToApp(uint32_t stackPointer, uint32_t address )
{
__asm volatile(" MSR msp, %[sp]\n"
" BX %[address] \n" : : [sp]"r"(stackPointer), [address]"r"(address) : "sp", "memory");
}

I tested also a call to the address of the main() of the second App from the main() of the first App but it triggers a HardFault too

uint32 * p = (uint32 *)0x100f02b1;
void (*fun_ptr)();
fun_ptr= (void *)p;
fun_ptr();

this is form the map file 

.text.startup.main
0x100f02b0 0x2a4 .\CortexM0p\ARM_GCC_541\Release\main_cm0p.o
0x100f02b0 main

the component is CY8C6347

When PSOC63 is master and 'useRxFifo' enabled we losing data within 28bytes if interrupts are disabled for more than 400msec or so.

Expected Data: 40011900031E030008000102038081828302D002FF020004881001AE

Received Data: 4001198302D002FF020004881001AEFFFFFFFFFFFFFFFFFFFFFFFFFF

When 'useRxFifo' is enabled the MCU suppose to receive up to 127 bytes on its own without intervention firmware right? Why are we seeing this effect for less than 32bytes?

We are planning to disable the useRxFifo, but want to understand just to make sure.

thanks your supports.

My name is david yu.

I sent a e-mail with the same subject in 2 July.

your reply is very helpful for me.

I also a little question about it.

1. the reflashing speed.

- I compared the two demon software, CE223726 in PSoC creator  and emWin_TFT_FreeRTOS in ModusToolbox.

when changing the image, PSoc creator is faster than modustoolbox. 

why PSoc creator is fast? I guess this  because of RTOS .

Can I speed up the speed changing a image  in RTOS?

2. the moving image

- I am trying to show the movie file in tft LCD using  the enWinGraphic example file.

but i couldn't do it.

would you tell me the example source code?

thanks

i copy the previous e-mail in below 

--------------------------------

Hi.

I am an engineer in Seoul, South Korea.

I got an PSoC6 Wifi BT Pioneer Kit with the TFT LCD 2.4 inch.

I am trying to work to show the sypress log  using the example source code of the CE225248_DisplayBuffer.

But I cannot.

Would you give me the information for this?

also can you give me the source of the sypress log showing in the TFT LCD?

I use the PSoC creater 4.4 version.

thanks

My E-mail : yugh@techrein.com

I'm trying to program a PSOC6 using a miniprog4 using JTAG.  The only option available is SWD.  I've got two PSOC6 on my board, SWD is only for a single device.

Why is the JTAG option grayed out?  I've updated firmware.  The same issue appears using the Pioneer kit.

Thanks.

Hello,
I am trying to set up a Dual-Core App on PSoC 6 BLE Prototyping Kit (CY8PROTO-063-BLE). While the Code on the M4 Core is currently only blinking the User LED on P6_3 i want the M0+ Core to send Data via SPI on SCB 1. The Code on the M0 Core is therefore initializing the SCB, GPIOs and Clocking and sends data and toggles another LED repeatedly. Unfortunately i can see the LEDs blinking (what means that both Cores are working) but the SPI does not send Data. 

This is the code running on the M0-Core:

#include "cy_pdl.h"

int main(void)
{

    /* Enable global interrupts */
    __enable_irq();

    /* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
    Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);

    //---------------- Config GPIO for LED -----------------------------------

	cy_stc_gpio_pin_config_t pinConfig = {
		/*.outVal =*/ 1UL,                  /* Output = High */
		/*.driveMode =*/ CY_GPIO_DM_PULLUP, /* Resistive pull-up, input buffer on */
		/*.hsiom =*/ P7_1_GPIO,             /* Software controlled pin */
		/*.intEdge =*/ CY_GPIO_INTR_RISING, /* Rising edge interrupt */
		/*.intMask =*/ 1UL,                 /* Enable port interrupt for this pin */
		/*.vtrip =*/ CY_GPIO_VTRIP_CMOS,    /* CMOS voltage trip */
		/*.slewRate =*/ CY_GPIO_SLEW_FAST,  /* Fast slew rate */
		/*.driveSel =*/ CY_GPIO_DRIVE_FULL, /* Full drive strength */
		/*.vregEn =*/ 0UL,                  /* SIO-specific setting - ignored */
		/*.ibufMode =*/ 0UL,                /* SIO-specific setting - ignored */
		/*.vtripSel =*/ 0UL,                /* SIO-specific setting - ignored */
		/*.vrefSel =*/ 0UL,                 /* SIO-specific setting - ignored */
		/*.vohSel =*/ 0UL                   /* SIO-specific setting - ignored */
	};

	(void) Cy_GPIO_Pin_Init(P7_1_PORT, P7_1_NUM, &pinConfig);
	Cy_GPIO_Inv(P7_1_PORT, P7_1_NUM);


	/*************PDL*****************/

	/* Allocate context for SPI operation */
	cy_stc_scb_spi_context_t spiContext;

	/* Master configuration */
	cy_stc_scb_spi_config_t spiConfig_master =
	{
	.spiMode = CY_SCB_SPI_MASTER,
	.subMode = CY_SCB_SPI_MOTOROLA,
	.sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
	.oversample = 10UL,
	.rxDataWidth = 8UL,
	.txDataWidth = 8UL,
	.enableMsbFirst = false,
	.enableInputFilter = false,
	.enableFreeRunSclk = false,
	.enableMisoLateSample = true,
	.enableTransferSeperation = false,
	.ssPolarity = CY_SCB_SPI_ACTIVE_LOW,
	.enableWakeFromSleep = false,
	.rxFifoTriggerLevel = 0UL,
	.rxFifoIntEnableMask = 0UL,
	.txFifoTriggerLevel = 0UL,
	.txFifoIntEnableMask = 0UL,
	.masterSlaveIntEnableMask = 0UL,
	};

	/* Assign pins for SPI master on SCB1: P10[0], P10[1], P10[2] and P10[3] */
	#define SPI_PORT_MASTER P10_0_PORT
	#define SPI_MOSI_NUM_MASTER P10_0_NUM
	#define SPI_MISO_NUM_MASTER P10_1_NUM
	#define SPI_SCLK_NUM_MASTER P10_2_NUM
	#define SPI_SS_NUM_MASTER P10_3_NUM
	

	/* Assign divider type and number for SPI */
	#define SPI_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
	#define SPI_CLK_DIV_NUM (0U)
	#define SPI_CLK_DIV_NUMBER_MASTER 5

	//Following is the settings for master

	(void) Cy_SCB_SPI_Init(SCB1, &spiConfig_master, &spiContext);

	/* Connect SCB1 SPI function to pins */
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_MISO_NUM_MASTER, P10_1_SCB1_SPI_MISO);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_MOSI_NUM_MASTER, P10_0_SCB1_SPI_MOSI);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_SCLK_NUM_MASTER, P10_2_SCB1_SPI_CLK);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_SS_NUM_MASTER, P10_3_SCB1_SPI_SELECT0 );

	/* Configure SCB1 pins for SPI Master operation */
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_MISO_NUM_MASTER, CY_GPIO_DM_HIGHZ);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_MOSI_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_SCLK_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_SS_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);


	/* Connect assigned divider to be a clock source for SPI */
	Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUM);

	/* SPI master desired data rate is 1 Mbps.
	* The SPI master data rate = (clk_scb / Oversample).
	* For clk_peri = 50 MHz, select divider value 5 and get SCB clock = (50 MHz / 5) = 10 MHz.
	* Select Oversample = 10. These setting results SPI data rate = 10 MHz / 10 = 1 Mbps.
	*/
	Cy_SysClk_PeriphSetDivider (SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER_MASTER, 4UL);
	Cy_SysClk_PeriphEnableDivider(SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER_MASTER);

	/* Enable SPI to operate */
	Cy_SCB_SPI_Enable(SCB1);

    for (;;)
    {
    	(void) Cy_SCB_SPI_Write(SCB1,0x9F);
    	Cy_GPIO_Inv(P7_1_PORT, P7_1_NUM);
    	Cy_SysLib_Delay(1023);
    }
}

Does anyone have an idea on how to fix this?

Best regards,
Marius 

Ideally, I would want two Analog mux components to toggle between Tx and Rx connections each (40 Tx and 40 Rx connections). The matrix button feature allows for a maximum of a 5x5 setup but using a multiplexer would allow me to toggle between the Tx and Rx connections. Is there any way to do this in PSoC6?

I am working with a PSOC6 bootloader all compilation goes without errors.

when I try to update the user application from PC cysmart I am getting the below error please do guide what is the cause for this error and how can I over come.

"The bootloader reported error 'Packet length invalid: the packet's length does not conform to the required packet format"

Is it possible to disable IMO in PSOC6 (assuming that clock HF clocked is switched to ECO like ALTHF)?

I didn't see any API (in PDL) that allows shutting it down.

  I think it was possible in PSOC4, and we did this for lower power (when running off ECO).

Hello, 

I did run a Benchmark with a Standard Matrix Multiplication Alogrithm on a CY8CKIT-062-BLE DEV Board.  I only made use of the Cortex M4 MCU. I ran the Benchmark 100 Times For Matrix Dimensions from 2x2 up to 100x100. I recorded the very First Execution time for each Dimension as well as the mean of the subsequent 99 executions. 
I observed the following behaviour: Up To a Dimension of about 30x30, the differente bestehen First Execution time and subsequent mean was rising up to 16 microseconds. From the Dimension 30x30 to 100x100, the difference rapidly dropped to around 2microseconds (with the First time being slower). 
Is there Any explanation for this Rapid drop? 
I do Not really Understand Why the difference Is Not continously growing with the Dimension?  
Thank you very much for your help.