PSoC 6 MCU

Trying to send a GATT notification with a payload of ~256 bytes between two BLE devices at 2Mbps.  If the devices are at a distance where the initial attempt to send the notification fails (for example, if the frame check sequence is ``bad" as indicated by a sniffer), should a packet sniffer show attempts to retransmit the notification occurring with each successive connection event until transmission succeeds (i.e. frame check sequence ``good")?  Is there any situation in which retransmission of a failed (i.e. unacknowledged) GATT notification does not occur during the very next device connection event (connection interval currently set to ~25ms), and if so, is there any firmware setting to control this time to retransmit? 

Hello all,

I am currently using a psoc CY8C6347BZI-BLD53 to do some very high speed SPI transfers at 25MHz and have come across some interesting behavior of the SPI FIFO. 

Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8. Upon further investigation with an oscilloscope there was some delay between transfers  (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.

The delay between each message becomes one clock cycle consistently when using Cy_SCB_WriteTxFifo() even while writing to the FIFO which solves my timing critical problem. However, I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38) . I found that if I add a delay of ~20 cycles after each call of Cy_SCB_WriteTxFifo() the right number of data (54) can be seen transferring on the oscilloscope before the next interrupt occurs.

I am reaching out for some help with trying to eliminate the added delay cycles after each Cy_SCB_WriteTxFifo, or at least to understand the root cause of why it work when they're there. I have looked into the TRM for the architecture, but they do not go into detail about FIFO operation. I don't have a usb right now so I can't post images from my oscilloscope but if you need them to understand I should have one by this Monday.

Your help is greatly appreciated!

I'm hoping somebody could please explain the pros and cons of running the PSOC 6 BLE stack on CM0 instead of CM4 like all sample code I've seen demonstrates. First of all, is running it on CM0 even possible? It seems to me that the BLE stack is a low load software module that should work equally well on either core. I would love it if somebody could point me to any appropriate (and current!) app notes and/or example projects.

I'm providing BLE programming expertise to a customer. I have only a few months of experience using the PSOC 6 BLE module so the core selection tradeoff is new to me.

Thanks - JJS

Hi all,

We have a CY8CKIT-064S0S2-4343W kit that we're trying to get up and running with the demonstration code that is generated from AWS. I'm following the getting started guide located here https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_psoc64.html and have successfully done everything up to the point of getting working code.

I've managed to build and flash the provided demo application, and the board successfully boots but then halts shortly after with "ERROR: stack overflow" — the attached screenshot shows what is happening. This happened with no WiFi credentials set, I then tried to set WiFi credentials and the error still happened. 

Any help in resolving this issue would be appreciated!

Hi:

   Why the device nane , the defined symbols field of C/C++ compiler can't change synchronously When I change the  devices from CY8C624ABZI-D44 to  CY8C624AAZI-S2D44? It will lead to a Mistake to inclde the header file of cy8c624abzi_d44.h!!!

Hello, 

I am very new to the world of BTLE, but have a large background in electrochemistry. I am currently curious about trying to power the PSOC6 purely off electrochemical reactions (glucose and glucose oxidase). I wold like to measure the potetnial over a resitior, or charge pump, or anyhting that would minimize power, and simply send that raw value via bluetooth in the lowest energy consuming form possible. I apologies if this is to vauge. If there is a simpler solution then the PSOC6 (from what i hear this is a very complex chip) i am all ears! 

thanks,

David Probst 

In PSoC 6 MCU with BLE: CY8C63x6, CY8C63x7 Architecture TRM, Document No. 002-18176 Rev. *H, section 25.6 SCB Interrupts, it says: "Note: To avoid being triggered by events from previous transactions, whenever the firmware enables an interrupt mask register bit, it should clear the interrupt request register in advance." I'm not sure what they are referring by "interrupt request register ." Would that be INTR_M?

In my mainline code, I have 

/* Unmasking only the spi done interrupt bit */
this->spi->base->INTR_M_MASK = SCB_INTR_M_SPI_DONE_Msk;

and in my ISR, 

	/* Mask the spi done interrupt bit */
	this->base->INTR_M_MASK &= ~SCB_INTR_M_SPI_DONE_Msk;

Is the Architecture TRM saying that before I unmask the SPI Done bit in INTR_M_MASK I should clear INTR_M? 

From PSoC 6 MCU: CY8C61x6, CY8C61x7 Registers TRM, Document Number: 002-23456 Rev. *C 1255, it looks like the SPI_DONE bit is RW1C. Should I do something like

	 /* Unmasking only the spi done interrupt bit */
    this->spi->base->INTR_M = SCB_INTR_M_SPI_DONE_Msk; // Clear request register; RW1C    
	this->spi->base->INTR_M_MASK = SCB_INTR_M_SPI_DONE_Msk;        

That doesn't seem quite right, because I'm only clearing one bit, but the TRM says I should "clear the interrupt request register." 

Hello,

I want to know the CPU current of the PSoC61 series, but the datasheet only has information about dual-core device (why?).

Please tell me the CPU current specifications for single-core products.

Regards,

Shimamura

Hello

Questions related to this thread.

https://community.cypress.com/t5/PSoC-6-MCU/The-contents-of-the-HEX-file-are-different/m-p/266218#M9358

Customer using CYBLE-416045-02.
Files built using PSoC Creator vary in size depending on the PC on which they are created.

(Version4.3)

As a verification, I built a sample program of "BLE_Alert_Notification" and compared customers HEX, but the size was different.
When I checked it with software that compares HEX files, I found data that existed in only one of them.

What is the cause of this?

Best Regards

Hayato

https://www.cypress.com/products/psoc-6-microcontrollers-32-bit-arm-cortex-m4m0

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