PSoC™ 6 Forum Discussions
Hello,
Question:What is the meaning of “Total Internal SRAM (Available) 1046528”
As the picture shows :
SRAM SIZE:1MB
Note:that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
SRAM The biggest theory :1024*1024=1048576(byte)
SRAM Actual maximum :1048576-2176=1046400(byte)
But,“Total Internal SRAM (Available) 1046528 ”
1046528-1046400=128(byte)
Where did this 128 bytes come from?
注:
best wishes,
JCD
Show LessOur SW development shall be done on CY8CKIT-062S2-43012 and we intend to demonstrate it on standalone CY8CMOD-062-43012 module i.e. no additional carrier board but only power supply from battery (currently we are not using any of the module peripheral buses)
1. Correct me if I wrong but from the schematics of both module and pioneer kit, we understand that both 3.6V (VBAT), 1.8V (VDDIO) and 3.3V (VDD) should be supplied to module?
2. For uploading new FW to CY8CMOD-062-43012 do we must use physical connectors (SWD / JTAG) or the default factory FW includes OTA capability?
Thanks in advance
Show Less
Hi,
Do we have any example of a ML deployment on PSoC 6 with sensing [read multiple sensors (ADC's )] and control [ex- PWM control, on/off etc] and communicating to external device like raspberry pi or local server for data logging/ continuous monitoring kind of IOT application.
Remote diagnostics for a level 3/4 IOT example with graphical interface at the PI etc, will be icing over the cake.
Best Regards,
Sunny
Show Less
Hello.
I am testing the gpio output speed with CY8CKIT-062-WIFI-BT.
I attached the source code based on the Modus Toolbox being tested.
The datasheet says that maximum GPIO speed is 100MHz, but it is measured around 10MHz.
Is there any way to make the output faster?
Thanks and Regards.
Show Less
Hello All,
I have a project using PSoC63 in which the Vdd (and Vdda) varies from 2.1 to 2.5 V. I am using the Scanning SAR ADC as follows:
- Differential input across a low impedance (shunt resistor).
- VRef is System Bandgap (1.2V).
- Input common mode voltage is near Vss.
It appears that, with a constant input voltage, as Vdd (Vdda) increases, ADC readings increase somewhat. I don't have actual numbers - this is simply a consistent pattern that I have observed.
Has anyone else seen this behavior? If so, do you have a fix?
Paul
Show LessHi, I am trying to follow the provisioning guide for the CY8KIT-064S0S2-4343W kit and I have encountered a problem that I cannot overcome.
I have followed the instructions on this guide but I can't go beyond the following command:
cysecuretools --policy ./policy/policy_multi_CM0_CM4_tfm.json --target CY8CKIT-064S0S2-4343W provision-device
This command results on this error:
2021-10-01 15:02:40,950 : C : ERROR : Early Production Units detected, please get earlier version of tools by running 'pip install --upgrade --force-reinstall cysecuretools==2.1.0'. Check the log for details
I have tried to install the 2.1.0 version as it shows on the result, but when I try to run again the first command, I get the following result.
2021-10-01 14:54:39,426 : C : ERROR : 'STATUS_PARTITION' is not one of ['SRAM_DAP', 'FLASH_PC1_SPM', 'FLASH_PC2', 'FLASH_PC3', 'FLASH_PC4', 'FLASH_MAIN_CODE', 'FLASH_MAIN_XO', 'FLASH_MAIN_DATA', 'FLASH_SUPERVISORY', 'FLASH_WORK_SECURE', 'FLASH_WORK', 'SRAM_PC0_PRIV', 'SRAM_PC0_PUB', 'SRAM_SPM_PRIV', 'SRAM_SPM_PUB', 'SRAM_PC1_PRIV', 'SRAM_PC2_PRIV', 'SRAM_PC3_PRIV', 'SRAM_PC4_PRIV', 'SRAM_MAIN', 'SMIF_CODE', 'SMIF_XO', 'SMIF_DATA', 'BOOT', 'UPGRADE']
Failed validating 'enum' in schema['properties']['boot_upgrade']['properties']['firmware']['items']['properties']['resources']['items']['properties']['type']:
{'enum': ['SRAM_DAP',
'FLASH_PC1_SPM',
'FLASH_PC2',
'FLASH_PC3',
'FLASH_PC4',
'FLASH_MAIN_CODE',
'FLASH_MAIN_XO',
'FLASH_MAIN_DATA',
'FLASH_SUPERVISORY',
'FLASH_WORK_SECURE',
'FLASH_WORK',
'SRAM_PC0_PRIV',
'SRAM_PC0_PUB',
'SRAM_SPM_PRIV',
'SRAM_SPM_PUB',
'SRAM_PC1_PRIV',
'SRAM_PC2_PRIV',
'SRAM_PC3_PRIV',
'SRAM_PC4_PRIV',
'SRAM_MAIN',
'SMIF_CODE',
'SMIF_XO',
'SMIF_DATA',
'BOOT',
'UPGRADE'],
'id': 'type',
'required': True,
'type': 'string'}
On instance['boot_upgrade']['firmware'][0]['resources'][3]['type']:
'STATUS_PARTITION'. Check the log for details
2021-10-01 14:54:39,426 : C : ERROR : Policy validation finished with error. Check the log for details
I have tried with different python versions and different OS (Windows 10 and Ubuntu 20.04) but I had the same result always.
I hope someone can help me. Thank you in advance.
Jon.
Show LessIs it possible to use the CY8KIT-028-EPD shield instead of the CY8CKIT-028-TFT for doing the Machine Learning Gesture Classification example? They both use the BMI160 IMU, but the example doesn't seem to work with the EPD shield.
Show LessWe have discovered a problem with the lwip library in ModusToolbox 2.0, 2.1, 2.2 and 2.3. It occurs when creating a new Wi-Fi project or updating the lwip library in an existing project. The problem is reported as a fatal error.
fatal: unable to access 'https://git.savannah.nongnu.org/git/lwip/': SSL certificate problem: certificate has expired
There is a defect in versions of OpenSSL prior to 1.1.0 which, as of September 30, causes web accesses with the Let's Encrypt intermediate certificate (Let's Encrypt R3) to fail. Let's Encrypt R3 contains signatures from two roots: DST Root CA X3 and ISRG Root X1. As explained by Let’s Encrypt (DST Root CA X3 Expiration), the former certificate has expired but the latter remains trusted. The defective versions of OpenSSL require both certificates to be trusted and erroneously deny the access.
OpenSSL 1.1.0 is used by the modus-shell utility on Windows hosts in all versions of ModusToolbox. The soon-to-be released ModusToolbox 2.4 shall include a newer version of OpenSSL to correct the problem.
To safely and reliably access lwip from ModusToolbox 2.3 and earlier, follow these steps to remove the expired certificate.
- Open the file ~\ModusToolbox\tools_2.x\modus-shell\etc\pki\ca-trust\extracted\pem\tls-ca-bundle.pem in a text editor
- Search for the line beginning with the comment "# DST Root CA X3"
- Delete that line and the associated certificate - including the "-----BEGIN CERTIFICATE-----" and "-----END CERTIFICATE-----" lines.
Hi, I am trying to wrap my head around a potential smartio use:
Goal: Deterministic cycling between three GPIO signals that control isolated FETs to toggle between three voltage levels on *one* output pin. To avoid shorts, only one signal may be high, and a dead time between switching would be helpful. In the end I'd like to have a function that enables the smartio voltage cycling like cycle_voltage(count,ontime,deadtime);
Signal pins: SIG_GND, SIG_MID, SIG_HIGH -> controlling the external 0V, 75V, 135V switching in my application:
SIG_HIGH=1 ________ 135V
| |
SIG_LOW=1 _______| | ______... 75V
| | |
SIG_GND=1 ____| |______ | 0V
Desired toggle behavior: 100-500uS signal high, then 0-1uS dead time, then signal high for next SIG_ pin.
Questions:
- I want to 1) cycle and 2) control signal high time for each signal and dead time from firmware. How do I think of this problem in terms of Chip inputs, clocks and perhaps chained LUTs?
- Can I link the SAR ADC's EOS trigger to start the smartio cycling?
- Alternatively, would it be possible in smartio to start the ADC on the first voltage cycling and snapshot scan every X cycles?
Thanks!