PSoC™ 6 Forum Discussions
Hello
How can I start multiple PWM together without using hardware trigger signal. In PSoC-4 we could do the following:
PWM_1_TriggerCommand(PWM_1_MASK | PWM_2_MASK, PWM_1_CMD_START);
This would start PWM_1 and PWM_2 simultaneously.
How can I do the same with PSoC-6?
Thanks
Show LessHi.
I'm trying to put my device to deep sleep using a 16 bit WDT (Counter0) . I'm able to put the device to deep sleep for 4ms.
1. However, when I try to increase the time to 30s by using a for loop, the device isn't going to deep sleep (current ~ 2mA).
2. Even when I use a 32 bit WDT ( Counter2), I get a current of about 2mA.
Can someone help me out with the code of putting the device to deep sleep for long intervals like 1-2 minutes and then wake up the device.
Thanks!
Show LessThe attached workspace bundle contains two projects: a bootloader minimally modified from CE216767, Bootloader_DevKit, and a very simple bootloadable, App_Stub_DevKit. I'm operating with PSoC Creator 4.2, PDL 3.1.4 (though 3.1.0 has the same issue), and the CYBLE-416045-EVAL dev kit.
The release build of the App Stub builds the App Stub against the bootloader's linker command files making it a standalone application in slot 0. Flash that into the part and it runs. The green LED on the dev kit is being operated by the M4 core and the red LED is being operated by the M0+ core at a different rate.
Fine so far.
Build the debug build of the bootloader and flash it into the part. The LED blinks white as it should.
Build the debug built of the App Stub. This is built against the App Stub's own linker command files which put it in slot 1. That build also creates the .cyacd2 file.
Use CySmart to load the App Stub .cyacd2 file via the bootloader. CySmart says it loads fine. The LEDs don't blink.
Problem: the application doesn't run.
Go into the App Stub's clock configuration and source Clk_HF0 from path 0 instead of path 1. Change nothing else. Rebuild the App Stub.
Reflash the bootloader into the board to destroy the broken App Stub. Note that I have disabled the button functionality of the bootloader since my real hardware doesn't have a usable button.
Use CySmart to load the rebuilt App Stub into the board. CySmart says it loads fine. The LEDs blink correctly.
For some reason, when the App Stub is in slot 0, the PLL clock works. When it's in slot 1, the PLL clock fails. Switching the App Stub to the FLL clock enables the App Stub to run in slot 1.
Help, please!
Show LessHi,
while porting WHD, I have similar question as https://community.infineon.com/t5/Wi-Fi-Combo/Support-for-porting-WHD-to-stm32F7/m-p/212755 .
1. However this question seems not answered fully. So, please let us know it.
2. & I assume the port specific type can be something like below -
e.g.
I setup the PSoC 62S4 Kit ADC , with 2 channels as singled end, Vref=VDDA, Vminus=VSSA. When feed the Vplus with known signal (or voltage) , the voltage readings of the two channel is ok and as expected. When I disconnected the signal, i.e. the Vplus open ended, I got reading (as calculated) is fixed as 2.8V . Is this normal? As I thought an open-ended Vplus will get varying readings from time to time, or at least the level is not so high.
Show LessHello Infineon Support,
Apologies, I originally posted about this issue here, but I was taken off the project before I was able to test it out. I'm back on now and I'm still getting this error after the BLE stack is initialized:
hci_open(): init error (0x4021c00)
The old post wouldn't let me reply so I'm adding some information here.
First off, I can confirm that I have the most up-to-date version of the BSP and libraries available, so that is not the issue.
Second, I'm using the Bluetooth_LE_CapSense_Buttons_and_Slider project as a baseline, and when I run that project, it works as expected and I do not get the HCI error.
For my project, I copied in the ble_task files and the design.cybt file, so my setup should be the same for all the bluetooth libraries and functions. I confirmed that my Makefile has the FREERTOS and WICED_BLE components added to it.
There's two other notable differences between my project and the original capsense project:
- My project is a dual core project, with a smaller app running on CM0P
- My project has some WiFi libraries it is using
Could either of those differences cause contention issues with the HCI hardware? I've tried all sorts of things to get this running but cannot shake this error message.
Best regards,
Cory
Show LessHi.
The most recent discussion on this topic dates back to 2018. At that point, Cypress did not support running FreeRTOS on the PSoC 6's CM0+ core.
First - has that position changed? Is there any official support for FreeRTOS on the CM0+?
Second - has anyone done this, especially using ModusToolbox? If so, would you please share your experience here?
A side issue is that the procedure for developing dual-CPU applications using ModusToolbox omits the FreeRTOS include directories from the compiler command line. The obvious brute-force workaround would be to add them in the CM0+ Makefile. Is there a better way?
There is a CM0 port of FreeRTOS available directly from FreeRTOS - download the FreeRTOS distro, then look in
<distro root>/FreeRTOS/Source/portable/<compiler>/ARM_CM0
The port is not specific to the PSoC 6, of course, and I'm unclear exactly what, if anything, needs to be changed.
For background, we plan to run FreeRTOS on both PSoC 6 cores. The CM0+ will handle data acquisition code (external multi-channel SPI ADC via DMA), and lightweight feature detection. The CM4 will be called into action for heavyweight processing when a feature is detected.
Thanks,
-Nick
Show LessHi Community,
Hope you are good. Did anyone has example of any temperature sensor with it's .c file written in freertos?
I am trying to write it but facing a problem. Can anyone help me on this ?
Regards,
Ali Shoaib
Show LessHey,
We are using PSOC6 CY8C6347BZI-BLD53 for our product. I am trying to add additional timer counter blocks (tcpwm) which will bring our in project use to 27 timers. The chip has 32 blocks available. I get this error upon enabling the 23rd timer block
E2810: The solution search limit for pin and fixed function block placement has been exceeded.
Attaching a screenshot for the full error. When I only have 22 timers, the error goes away so I know it is the TCPWM block and no other components.
Is there a way to know if the other blocks are used elsewhere internally? We have BLE enabled alongwith several other blocks including wdt, spi, i2c, uart etc.
Thanks in advance,
Vandita
Show Less