PSoC™ 6 Forum Discussions

Hi,

I am wondering if there would be a function/method to trigger auto-calibration for CSX when there's an apparent change in baseline capacitance (goes up from 1pF to 2.5pF for example)?

Thank you!

What is the main advantage of having an arduino shield compatible pins  along with the PSoc pioneer kit and how does it help in an application where we want to impliment several Serial Communication Blocks to interface around 14 sensors to bild an Agri station.

Hi,

The following is our understanding of the PSoC 6 datasheet, could anyone check if this is correct?

If Sensor Auto-Reset is enabled, the baseline follows the raw count

If Sensor Auto-Reset is disabled, the baseline will/will not reset depending on the following conditions:

1. For Noise threshold:
   1. If the baseline < raw count < (baseline + noise threshold), the baseline will reset with the raw count.
   2. If raw count > (baseline +noise threshold), the baseline will not reset.
2. For Negative Noise threshold and low baseline reset:
   1. If (baseline - negative noise threshold) < raw count < baseline, the baseline will reset with the raw count.
   2. If Raw count < (baseline - negative noise threshold) for a number of samples more than the low baseline reset, the baseline will reset with the raw count.
   3. If Raw count < (baseline - negative noise threshold) for a number of samples less than the low baseline reset, the baseline will not reset.

On top of that, I was wondering if the Noise threshold and Negative Noise threshold are in terms of percentage of the baseline or an absolute number.

Thank you in advance for your help. Have a great day!

Hello all,

I am using the CY8CKIT-062S4 PSoC6 kit for I2C communication with a device. In this case, the PSoC6 kit is an I2C master device and the other device is an I2C slave.|

Now, coming to the problem, actually, the I2C slave device is already having the pull-up resistors to 3.3V. 

as you can see in the above picture. Now, I am connecting the PSoC 6 device to this device using the J20 pin header as J20.1 to Vcc (3.3V), J20.2 as SCL, J20.3 as SDA, and J20.4 as GND (0V).

As the slave device is already having the pull-up resistors so, I am initializing the PSoC6 SCB0 block as follows (using the PDL library),

Cy_GPIO_SetDrivemode(I2C_Channel_SCL_PORT, I2C_Channel_SCL_NUM, CY_GPIO_DM_OD_DRIVESLOW);
Cy_GPIO_SetDrivemode(I2C_Channel_SDA_PORT, I2C_Channel_SDA_NUM, CY_GPIO_DM_OD_DRIVESLOW);

The problem with the interface of this I2C slave is that the I2C master should support the I2C multi-master to interface this slave device. But the thing is that I haven't seen any words which show that this PSoC kit microcontroller supports I2C multi-master.

Now, coming back to the real problem, after successfully initializing the I2C block of the PSoC 6 device, when I am trying to write to the slave device, after writing one byte of data, the I2C master remains busy, I didn't get the I2C_MASTER_WRT_COMPLETE callback also, after writing that, the SDA pin keeps low and never high, so after that, I am unable to do anything, please help me to resolve the problem.

I am initializing the I2C at 400kbps and config is as follows: 
.i2cMode = CY_SCB_I2C_MASTER,
.useRxFifo = false,
.useTxFifo = true,
.slaveAddress = 0U,
.slaveAddressMask = 0U,
.acceptAddrInFifo = false,
.ackGeneralAddr = false,
.enableWakeFromSleep = false,
.enableDigitalFilter = false,
.lowPhaseDutyCycle = 16,
.highPhaseDutyCycle = 9,

The I2C read and write of the I2C slave are as follows:

Thank you.

Regards,
Vivek Karna

readVal  =  Cy_GPIO_Read(P12_0_PORT,  P12_2_PIN);

readVal = Cy_GPIO_Read((GPIO_PRT_Type *)base , pin);

The MCU I use is CY8c6136.
I am using Cy_GPIO_Read().

 - readVal = Cy_GPIO_Read(P12_0_PORT, P12_2_PIN);
I can do this when I know the port information of the corresponding pin.

If I do not know the port information of the pin, I am wondering how to enter the port information.

Port mapping is done in modus_toolbox,
This problem occurred while porting from another MCU.
May I get some information about this?

 thanks.

Hi,

I'm studying the schematic of CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit. Level shifters (U10, U12) have been used between PSoC5LP (KitProg) and PSoC 6 because of different voltage domains (P5LP_VDD and VTARG). Affected signals:

P5LP1_6 <-> UART_RTS  (U10)
P5LP15_5 <-> UART_CTS (U12)

I'm now asking myself why Cypress/Infineon has chosen U12 instead of routing VTARG directly to VDDIO2 of PSoC5LP.

Similar considerations also apply for CY8CKIT-062-BLE (PSoC 6 BLE Pioneer Board), where level translater U13 has been used for SPI and UART. Here, SPI_MISO signal (KitProg SIO pin P12[5]) has been routed via U13, although SIO pin has Vref-feature and P5LP_SIO_VREF = VTARG_MON = P6_VDD ( != 5V).

I'm happy about every idea.

Michael

Hello all,

I am using CY8CKIT-062S4 PSoC 6 kit for development purposes.

In that kit, due to unavailability of the digital input pins, I have to use the Analog pins of the controller. So due to that, I am using P10.5 and P10.6 pins as digital input pins.

I have configured these pins as follows:

.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = UserLapSel_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,

I don't want to enable interrupt, so I have disabled it, after using Cy_GPIO_Pin_Init(GPIO_PRT10, 5U, &UserLapSel_config).

But after initializing the GPIO, when I am reading the state of GPIO, it is not able to sense the 3.3V digital input. 

I have read on the forum that I have enabled some other functionalities specifically for this Analog specialized pin using HSIOM, but I am unable to do that. Please suggest to me what things do I need to operate this P10.5 to read as a digital input pin?

Thank you.

Regards,
Vivek Karna

I have been using PSoC-6 (CY8CPROTO-063-BLE) for years. I need to use a PSoC that supports SD-Cards in the SD mode, not the SPI mode.

What is the PSoC that provides SD-Card interface and is closest to PSoC-6, so that migration is less painful ?

thanks

Hello,
I'm testing UART(P5.0, P5.1) on CY8CKIT-062-WIFI-BT.

When I execute soft reset through NVIC_SystemReset(), UART Tx(P5.1) goes low for a while.
For this reason, the PC terminal utility receives 1 byte (0x00).
Is there any way to keep the UART Tx line high even after soft reset?

Thanks and Regards,
YS