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PSoC 6 MCU

GaLo_4308236
New Contributor II

Based on the original closed thread here: Best path using DMA to transfer 100kB from sram into tcpwm configured PWM?

Progress:

So now I've got DMA transferring the big array into the TCPWM's capture register.

Any tips on what is needed to have DMA play nice with the TCPWM's TCPWM_CNT_CC_BUFF register and the buffering features it provides?

Also hoping someone can stop me if this is madness, but I'm clocking everything at 100MHz no dividers.

CLK_FAST,CLK_PERI, CLK_SLOW (and thus DMA), and the clock for the TCPWM all 100MHz.

Will I be able to reliably use the triggering features considering the above?

JimT_21

aceh_327141

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1 Solution
GaLo_4308236
New Contributor II

I had been using the period swap option however,

I had been assuming the x loop increment count was continuing to increment beyond 256 for each Y loop.

Reading the pseudo-code provided in the technical reference manual is what made it click for me.

Nested for loop and the inner loop re-initializes x to 0 for each iteration of the outer loop.

Setting the Y loop increment to 256 immediately gave me the results I wanted.

I'm not near the sources at the moment but I will post the configuration I used as the answer to this question.

View solution in original post

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5 Replies
GaLo_4308236
New Contributor II

static void configureDma(uint16_t *descriptor0SourceAddress)

{

    /* Configure DMA Descriptor to change the PWM compare value per provided buffer */

    dmaDescriptorPwmLed0.srcAddress = (void *) descriptor0SourceAddress;

    dmaDescriptorPwmLed0.dstAddress = (void *) &(PWM_LED_HW->CNT[PWM_LED_NUM].CC_BUFF);

    dmaDescriptorPwmLed1.srcAddress = (void *) dmaDescriptorPwmLed0.srcAddress + (256 * 256);

    dmaDescriptorPwmLed1.dstAddress = (void *) &(PWM_LED_HW->CNT[PWM_LED_NUM].CC_BUFF);

    Cy_DMA_Descriptor_Init(&DMA_PWM_LED_Descriptor_0, &dmaDescriptorPwmLed0);

    Cy_DMA_Descriptor_Init(&DMA_PWM_LED_Descriptor_1, &dmaDescriptorPwmLed1);

    /* Initialize DMA channel */

    Cy_DMA_Channel_Init(DMA_PWM_LED_HW, DMA_PWM_LED_CHANNEL, &DMA_PWM_LED_channelConfig);

    /*  Enables DMA channel interrupt mask */

    Cy_DMA_Channel_SetInterruptMask(DMA_PWM_LED_HW, DMA_PWM_LED_CHANNEL, CY_DMA_INTR_MASK);

    /* Enable DMA Channel */

    Cy_DMA_Channel_Enable(DMA_PWM_LED_HW, DMA_PWM_LED_CHANNEL);

    /* Enable DMA hardware block */

    Cy_DMA_Enable(DMA_PWM_LED_HW);

}

Writing to .CC_BUFF now but not sure what triggers to use and how they'll resolve.

Current failing approach is:

PWM Trigger output on OVERFLOW -> DMA trigger input     and    DMA trigger output -> PWM trigger input SWAP

I get the feeling the above approach is too naive to be true and that I might need another DMA channel?

Next I'll probably start adjusting clocks to something more sane to ensure the triggers have enough time to be caught per the technical reference.

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AchimE_41
Employee

Hi,

try the overflow to trigger both the TCPWM swap as well as the DMA start. The DMA will start the data transfer with a few clock cycles delay (as mentioned in the Architecture TRM) leaving the TCPWM enough time to swap out the data.

Achim

AchimE_41
Employee

Or just use the "Enable Period Swap" option in the component configuration.

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GaLo_4308236
New Contributor II

I had been using the period swap option however,

I had been assuming the x loop increment count was continuing to increment beyond 256 for each Y loop.

Reading the pseudo-code provided in the technical reference manual is what made it click for me.

Nested for loop and the inner loop re-initializes x to 0 for each iteration of the outer loop.

Setting the Y loop increment to 256 immediately gave me the results I wanted.

I'm not near the sources at the moment but I will post the configuration I used as the answer to this question.

View solution in original post

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GaLo_4308236
New Contributor II

If I don't answer this this weekend consider it answered.

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