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PSoC 6 MCU

JoYa_4324706
New Contributor II

Hi,

I am using the example CE220060 - Watchdog Timer and trying to move the code from M4 to M0. It works on M4 but however not on M0. The watchdog timer interrupt handler was never called on M0. The attached is the example with simple modification of moving M4 code to M0. Are there any other settings required that I have missed in my example? Thanks!

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1 Solution
NoriakiT_91
Employee

An interrupt initialization structure WDT_IRQ_cfg is declared as follows.

/* WDT interrupt configuration structure */

const cy_stc_sysint_t WDT_IRQ_cfg = {

    .intrSrc = (IRQn_Type)WDTIsr_INTC_CORTEXM0P_ASSIGNED,

    .intrPriority = WDT_IRQ__INTC_CORTEXM0_PRIORITY

};

The initialization configuration structure cy_stc_sysint_t is different in Cm0+ and CM4.  Following declaration is contained in the cy_sysint.h file.

/**

* Initialization configuration structure for a single interrupt channel

*/

typedef struct {

    IRQn_Type       intrSrc;        /**< Interrupt source */

#if (CY_CPU_CORTEX_M0P)

    cy_en_intr_t    cm0pSrc;        /**< (CM0+ only) Maps cm0pSrc device interrupts to intrSrc */

#endif

    uint32_t        intrPriority;   /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */

} cy_stc_sysint_t;

If you want to declare an interrupt for CM0+ the cm0Src field must be specified.

Anyway, I confirmed that this structure is not required.  My solution is as follows.

    /* Step 6 - Enable interrupt if periodic interrupt mode selected */

    #if(WDT_DEMO == WDT_INTERRUPT_DEMO)

        Cy_SysInt_Init(&WDTIsr_cfg, WdtInterruptHandler);

        NVIC_EnableIRQ(WDTIsr_cfg.intrSrc);

        Cy_WDT_UnmaskInterrupt();

    #endif

Please change the step 6 to use the WDTIsr_cfg structure instead of the WDT_IRQ_cfg.

Regards,

Noriaki

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2 Replies
NoriakiT_91
Employee

An interrupt initialization structure WDT_IRQ_cfg is declared as follows.

/* WDT interrupt configuration structure */

const cy_stc_sysint_t WDT_IRQ_cfg = {

    .intrSrc = (IRQn_Type)WDTIsr_INTC_CORTEXM0P_ASSIGNED,

    .intrPriority = WDT_IRQ__INTC_CORTEXM0_PRIORITY

};

The initialization configuration structure cy_stc_sysint_t is different in Cm0+ and CM4.  Following declaration is contained in the cy_sysint.h file.

/**

* Initialization configuration structure for a single interrupt channel

*/

typedef struct {

    IRQn_Type       intrSrc;        /**< Interrupt source */

#if (CY_CPU_CORTEX_M0P)

    cy_en_intr_t    cm0pSrc;        /**< (CM0+ only) Maps cm0pSrc device interrupts to intrSrc */

#endif

    uint32_t        intrPriority;   /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */

} cy_stc_sysint_t;

If you want to declare an interrupt for CM0+ the cm0Src field must be specified.

Anyway, I confirmed that this structure is not required.  My solution is as follows.

    /* Step 6 - Enable interrupt if periodic interrupt mode selected */

    #if(WDT_DEMO == WDT_INTERRUPT_DEMO)

        Cy_SysInt_Init(&WDTIsr_cfg, WdtInterruptHandler);

        NVIC_EnableIRQ(WDTIsr_cfg.intrSrc);

        Cy_WDT_UnmaskInterrupt();

    #endif

Please change the step 6 to use the WDTIsr_cfg structure instead of the WDT_IRQ_cfg.

Regards,

Noriaki

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VenkataD_41
Moderator
Moderator

Hi,

Please refer the PSoC 6 MCU interrupts application note for more information (link given below).

https://www.cypress.com/documentation/application-notes/an217666-psoc-6-mcu-interrupts

Thanks

Ganesh

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