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PSoC 6 MCU

Anonymous
Not applicable

Hello, I am facing a problem with deep sleep integration and hope that someone could help. I am working on a project right now that uses only the cm0 core of the psoc 6 and part of the project uses the i2c bus to sample from an accelerometer to send data across bluetooth. I've also used the MCWDT as a master timer to control multiple virtual timers, one of them configured for the accelerometer at its sampling rate.

The problem is that the core occasionally fails to enter deep sleep mode (measured by toggling different GPIO pins depending on the result of deep sleep API) when enabling the MCWDT (should note MCWDT can wake up core from deep sleep). However the problem doesn't occur when disabling the MCWDT i.e. just having Bluetooth enabled.

I've checked documentation for handling MCWDT before entering low power modes but could not come up with any results. What is recommended to fix the problem? Thank you.

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1 Solution
Moderator
Moderator

Is it possible CPU is waked up immediately after entering DSM, just because of the interrupt triggered from MCWDT?

The time under DSM maybe too short to make GPIO toggling visible.

You can verify it by printing the return value of DSM entering API.

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3 Replies
Moderator
Moderator

Is it possible CPU is waked up immediately after entering DSM, just because of the interrupt triggered from MCWDT?

The time under DSM maybe too short to make GPIO toggling visible.

You can verify it by printing the return value of DSM entering API.

View solution in original post

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Anonymous
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Hi fwan, thanks for your reply. I am verifying the results of the API by toggling different GPIO pins depending on the success of deep sleep transition. Your speculation is a possibility. Would it be normal for deep sleep transition to return unsuccessful if the MCWDT interrupt triggers while the CPU is in the process of going to deep sleep mode?

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Moderator
Moderator

Generally the interrupts are disabled in DSM entering API. If there is WDT interrupt during entering DSM, it would be pending until DSM is entered. And then this interrupt would wake-up the core from DSM to feed WDT in ISR.

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