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PSoC 6 MCU

semcc_4006746
New Contributor

Hi,

I'm trying to evaluate if the PSoC 63/62 is a good choice for my project. I was initially attracted to this family due to the high MCU clock which fit my minimum timing requirements.  I'm interested in calculating a round-trip time between SCAN_REQ and SCAN_RSP on the MCU.  I've been trying to find information on the clock speeds for the BLE subsystem. I found in the product specifications:

Note that at Cortex M4 speeds above 100 MHz, the M0+ and Peripheral subsystem are limited to half the M4 speed. If the M4 is running at 150 Mhz, the M0+and peripheral subsystem is limited to 75 MHz

Does this imply BLE subsystem operates at 100/75 MHz?

If anyone has any other AN suggestions for a high freq timer to accomplish this I'm all ears.

Thanks,

Sean

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1 Solution
ShipingW_81
Moderator
Moderator

The clock source for BLE subsystem is BLE ECO, which feeds the link layer controller and the radio Phy, and it is relatively independent from the clocking system of main system.

The frequency of BLE ECO is fixed at 16MHz or 32MHz, see device datasheet page#52 - http://www.cypress.com/file/385921/download

Therefore, you may not be able to achieve the BLE clock as high as the clock source of the cores.

View solution in original post

1 Reply
ShipingW_81
Moderator
Moderator

The clock source for BLE subsystem is BLE ECO, which feeds the link layer controller and the radio Phy, and it is relatively independent from the clocking system of main system.

The frequency of BLE ECO is fixed at 16MHz or 32MHz, see device datasheet page#52 - http://www.cypress.com/file/385921/download

Therefore, you may not be able to achieve the BLE clock as high as the clock source of the cores.

View solution in original post

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