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PSoC 6 MCU

Anonymous
Not applicable

Hi,

I am trying to trigger an interrupt on MC4 using IPC notify on CM0+.

I am failing to verify that the interrupt is indeed triggered on CM4.

Here is what I am doing:

  • I am using the Dual Core Shared Memory example code as my basic code.
  • On MC0+ (main_cm4.c):
    • Enabling interrupts: __enable_irq();
    • Mask (enable) interrupts:

                    IPC_INTR_STRUCT_Type *myIpcHandleInt;

                    myIpcHandleInt = Cy_IPC_Drv_GetIntrBaseAddr(MY_IPC_CHANNEL);

                    Cy_IPC_Drv_SetInterruptMask (myIpcHandleInt, 0xFFFF, 0xFFFF);

    • Sending 1 as the notification event interrupt to Cy_IPC_Drv_SendMsgPtr(): Cy_IPC_Drv_SendMsgPtr(myIpcHandle, 0x1ul, &sharedVar)
  • On CM4 (main_cm4.c):
    • Enabling interrupts: __enable_irq();
    • Enabling IPC IRQ: NVIC_EnableIRQ(41); // 41 denotes CPUSS Inter Process Communication Interrupt #0
    • Mask (enable) interrupts:

               IPC_INTR_STRUCT_Type *myIpcHandleInt;

               myIpcHandleInt = Cy_IPC_Drv_GetIntrBaseAddr(MY_IPC_CHANNEL);

               Cy_IPC_Drv_SetInterruptMask (myIpcHandleInt, 0xFFFF, 0xFFFF);

I am trying to verify the interrupt indeed occurred by using the debugger on CM4, and placing a break-point at the Default_Handler (startup_psoc63_cm4.S).

What am I missing?

** The project is attached.

Use CE216795_DualCoreSharedMemory01.cyprj as the project file.

Thanks

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1 Solution
Employee

You could also use the IPC Pipes or Semaphore layer APIs that comes with the PDL.

This layer makes very easy to handle synchronization and messages between the cores.

We are creating a code examples to show off how to use them. From now, you can refer to the PDL documentation.

View solution in original post

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6 Replies
New Contributor II

Hello,

I will be easier for the community to help you if you share your project (just make a minimal archive of your project with PSoC Creator).

Could you share your project?

A topic with a similar problem (interrupt not occurred with dual application) reveals that : "The reason for this fix is that the vector table on the CM4 must be 0x400 aligned."

You check this point.

yours,

Robin.

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Anonymous
Not applicable

Thanks Robin.

I have now attached the project to the original message.

Use CE216795_DualCoreSharedMemory01.cyprj as the project file.

Thanks

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Anonymous
Not applicable

Some more information:

When I manually set IPC_INT_1 to PENDING [ NVIC->ISPR[1] |= 0x400; ], I do manage to stop with the debugger at the Default_Handler in CM4.

It means that the interrupt table is ok, and the interrupt itself is enabled.

Still, when using IPC to trigger the same interrupt, the debugger won't stop on the Default_Handler, that is, the interrupt is not really triggered.

According to the INTR_MASK register, the notification has passed to CM4, and the mask is enabled.

Any clue would be great

Thanks

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New Contributor II

Hi,

I have written program where CM0+ trigger interrupt in CM4 using IPC notify and sends pointer, while CM4 after reading pointer trigger interrupt in CM0+ using IPC release.

Let me know if this helps.

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Employee

You could also use the IPC Pipes or Semaphore layer APIs that comes with the PDL.

This layer makes very easy to handle synchronization and messages between the cores.

We are creating a code examples to show off how to use them. From now, you can refer to the PDL documentation.

View solution in original post

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Moderator
Moderator

Currently we have three code examples which you may find helpful;

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