PSoC 6 MCU

[CoreyW_81]

Can you let me know if there is a document for the PCB routing the 116 or 128 BGA package for a four layer board?  I’m not sure if this can be done.

If there is a reference layout that can be used by customers, that would be appreciated.

The customer wants to keep the board technology simple, so if we can provide something with 4 layers, without vias in pads, and without any blind or buried vias, that would be ideal.

[ShipingW_81]

I do not see any P6 BGA design with 4 layers. The simplest one is 6 layers(CY8CMOD-062-4343W). It's attached here.

4 layers sounds pretty tough for this package.

[ThSt_1053481 · Accepted solution]

I agree with Wang that four layers sound too few for a BGA. It all depends on the number of IOs you need to connect to the chip.

Check out the following two app notes on calculating the number of layers and design guidelines for PCBs using BGA packages:

• https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf
• http://www.ti.com/lit/an/sprabb3/sprabb3.pdf

As to what regards not using vias in pads, this is entirely possible, but your PCB manufacturer needs to support small clearances.

[CoreyW_81]

Looks like we might be able to break out the signals on 2-3 layers based on the CY8CMOD-062-4343W design and the guidance in the Xilinx application note. The 2 outer rows can break out easy, the 2nd row of 40 pins can break out on the same layer as there are 48 routing channels available.  Then you only need to break out 36 internal pins on 1 additional layer

So while it might not be optimal nor simple, it does look possible.

Comments?

[ShipingW_81]

Yes, it might be possible though the work looks not easy.