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PSoC 6 MCU

Anonymous
Not applicable

Hello,

There are three type of register for controlling protection context.

They are MPUx_MS_CTL.PC, SMPU_MSx_CTL.PC_MASK_15_TO_1 and SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1.

1) MPUx_MS_CTL.PC

I think this register select protection context of a master which is assigned by each register. That is, Master work as protection context # indicated by PC.

If MPU0_MS_CTL.PC is 3, a program on CM0+ work as protection context 3. If CM0+ try to access an area except protection context 3. the area of protection context 3 is set by SMPU_STRUCTURE_ADDRx register.

2) SMPU_MSx_CTL.PC_MASK_15_TO_1

I think this register select SMPU Structure assigned by protection context of SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1 which SMPU can control.

3) SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1

I think this register indicate each SMPU Structure of protection context which is set by PC_MASK_15_TO_1

If my understanding is wrong, please correct it

Best regards,

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1 Solution
MeenakshiR_71
Employee

Hello,

1) Yes your understanding of the MPUx_MS_CTL register is correct. MPUx_MS_CTL.PC sets the Protection context for the associated master. In PSoC 6, CM0+(MPU0), CM4 (MPU14) and Crypto (MPU1) have MPUs that is available for the users.

2)  SMPU_MSx_CTL.PC_MASK_15_TO_1 identifies what protection contexts can be programmed for the associated bus master.

  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x0004, MPU0_MS_CTL.PC[] can be set to only “3”.
  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x0000, PC[] cannot be changed.
  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x7FFF, PC[] can be changed to any value (except 0).

There are 5 SMPU bus masters available in PSoC 6 - CM0+ (SMPU0), Crypto (SMPU1), DW0 (SMPU2), DW1(SMPU3) and CM4(SMPU14). For the SMPU masters that do not have MPUx_MS_CTL register like DW blocks, the PC value is inherited from the bus master that configures and starts the DW.

3) SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1 identifies which protection contexts get access the memory/address region protected by the particular SMPU structure. Any bus master that has a matching ATTx value will gain access to the region guarded by the particular SMPU. There are a total of 16 SMPU structures in PSoC 6.

I hope this clarifies the protection context fields across the device

I understand this is a bit difficult to grab at first, we are working on a security application note and it will be out soon and will clear most of the confusions around protection contexts and their usage.

Let me know if this helps in the interim

Regards,

Meenakshi Sundaram R

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1 Reply
MeenakshiR_71
Employee

Hello,

1) Yes your understanding of the MPUx_MS_CTL register is correct. MPUx_MS_CTL.PC sets the Protection context for the associated master. In PSoC 6, CM0+(MPU0), CM4 (MPU14) and Crypto (MPU1) have MPUs that is available for the users.

2)  SMPU_MSx_CTL.PC_MASK_15_TO_1 identifies what protection contexts can be programmed for the associated bus master.

  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x0004, MPU0_MS_CTL.PC[] can be set to only “3”.
  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x0000, PC[] cannot be changed.
  • If SMPU_MS0_CTL.PC_MASK_15_TO_1 is 0x7FFF, PC[] can be changed to any value (except 0).

There are 5 SMPU bus masters available in PSoC 6 - CM0+ (SMPU0), Crypto (SMPU1), DW0 (SMPU2), DW1(SMPU3) and CM4(SMPU14). For the SMPU masters that do not have MPUx_MS_CTL register like DW blocks, the PC value is inherited from the bus master that configures and starts the DW.

3) SMPU_STRUCTUREx_ATTx.PC_MASK_15_TO_1 identifies which protection contexts get access the memory/address region protected by the particular SMPU structure. Any bus master that has a matching ATTx value will gain access to the region guarded by the particular SMPU. There are a total of 16 SMPU structures in PSoC 6.

I hope this clarifies the protection context fields across the device

I understand this is a bit difficult to grab at first, we are working on a security application note and it will be out soon and will clear most of the confusions around protection contexts and their usage.

Let me know if this helps in the interim

Regards,

Meenakshi Sundaram R

View solution in original post

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