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PSoC 6 MCU

JeHu_3414236
Contributor II

I am using VDDD=3.3V, VDDIO0,VDDIO1,VDDA=1.8V, 1.1V LDO internal regulator, no external crystals and the deep sleep current is 15uA higher than in hibernate mode on my custom board.  I am retaining all RAM.  According to the datasheet deep sleep current IDD33B_B is 9uA and hibernate current IDD34A is 800nA so the difference should be 8uA.  Why is there a 7uA difference between the spec and the measurements?  I am entering deep sleep and hibernate with these functions:

Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);

Cy_SysPm_Hibernate();

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1 Solution
Rakshith
Moderator
Moderator

Hi JeHu_3414236,

Is the spec wrong or is there something wrong with the deep sleep driver?

The datasheet values are tested with MCU ICs and processor modules. Are you using a custom board? There could be leakage current on the custom board. If you are testing this on a development Kit can you try removing the resistor R86 as mentioned here - Community-Code-Examples/README.md at master · cypresssemiconductorco/Community-Code-Examples · GitHu...

Do I need to disable other blocks manually before calling Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)

Yes if any of the hardware blocks are used it needs to be disabled manually. Apart from these are you using PLL/FLL? If yes, can you disable all higher frequency clocks? Can you also select GPIO as Debug Select in the System tab of cydwr file? If you are using the GPIO pins, then they should be in a high impedance state.

Please let me know your observations.

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B

View solution in original post

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13 Replies
Rakshith
Moderator
Moderator

Hi JeHu_3414236​,

Can you please let me know if you are using PSoC Creator or ModusToolbox? We have an example project for ModusToolbox and you can check it out here - Community-Code-Examples/mtb_training/session05/mtb_05_ex04_hibernate at master · cypresssemiconducto...

Also, can you try switching to BUCK regulator?

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B
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JeHu_3414236
Contributor II

I am using PSoC Creator.  The current in deep sleep is 7uA higher when I use buck.  Is the spec wrong or is there something wrong with the deep sleep driver?  Do I need to disable other blocks manually before calling Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)?  I already disabled all peripherals like SPI and UART.

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Rakshith
Moderator
Moderator

Hi JeHu_3414236,

Is the spec wrong or is there something wrong with the deep sleep driver?

The datasheet values are tested with MCU ICs and processor modules. Are you using a custom board? There could be leakage current on the custom board. If you are testing this on a development Kit can you try removing the resistor R86 as mentioned here - Community-Code-Examples/README.md at master · cypresssemiconductorco/Community-Code-Examples · GitHu...

Do I need to disable other blocks manually before calling Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)

Yes if any of the hardware blocks are used it needs to be disabled manually. Apart from these are you using PLL/FLL? If yes, can you disable all higher frequency clocks? Can you also select GPIO as Debug Select in the System tab of cydwr file? If you are using the GPIO pins, then they should be in a high impedance state.

Please let me know your observations.

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B

View solution in original post

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JeHu_3414236
Contributor II

I am using a custom board.  I created a new PSoC Creator project with no debug pins, no clocks except PILO and nothing but GPIO pins to initialize hardware for lowest current.  This is the program I run:

cy_stc_syspm_callback_params_t clkCallbackParams = {

        /*.mode       =*/ CY_SYSPM_CHECK_READY,

        /*.base       =*/ NULL,

        /*.context    =*/ NULL

    };

   

    cy_stc_syspm_callback_t clkCallback = {

        /*.callback   =*/ &Cy_SysClk_DeepSleepCallback,

        /*.type       =*/ CY_SYSPM_DEEPSLEEP,

        /*.skipMode   =*/ CY_SYSPM_SKIP_CHECK_FAIL | CY_SYSPM_SKIP_BEFORE_TRANSITION,

        /*.callbackParams =*/ &clkCallbackParams,

        /*.prevItm    =*/ NULL,

        /*.nextItm    =*/ NULL

    };

   

int main(void)

{

    __enable_irq(); /* Enable global interrupts. */

while (1)

{

Cy_SysClk_FllDisable();

Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);

}

}

There is no change to the deep sleep current.  When I call Cy_SysPm_Hibernate(), it is still 15uA less than calling Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT).

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JeHu_3414236
Contributor II

I tried changing power mode to 0.9V buck and current goes down 3uA in deep sleep.  When I try to use 0.9V buck in the real project, I get an error that I cannot use peripheral clock > 25MHz.  I am using USB which requires 48MHz clock.  Is it possible to set to 0.9V buck before going to deep sleep and setting to 1.1V LDO when exiting deep sleep?  I will not go to deep sleep when USB is being used.  Can you give me the source code for doing this for PSoC Creator using PDL 3.0.4?

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JeHu_3414236
Contributor II

I changed the power mode to use 1.1V buck normally and 0.9V buck during deep sleep.  It seems to be working when I switch modes like this but I don't think it is correct:

Cy_SysPm_SimoBuckSetVoltage1(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V);

Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);

Cy_SysPm_SimoBuckSetVoltage1(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V);

I tried to register a deep sleep callback handler and set buck voltage there but the current does not go down in deep sleep:

cy_en_syspm_status_t deep_sleep_check(cy_stc_syspm_callback_params_t *callbackParams)

{

if (callbackParams->mode == CY_SYSPM_BEFORE_TRANSITION)

Cy_SysPm_SimoBuckSetVoltage1(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V);

else if (callbackParams->mode == CY_SYSPM_AFTER_TRANSITION)

Cy_SysPm_SimoBuckSetVoltage1(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V);

return CY_SYSPM_SUCCESS;

}

I did not change flash wait states or clock frequency.  Can you show me the correct way to switch buck voltage for deep sleep mode?  I attached my cyfitter_cfg.c with clock settings I use.

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Rakshith
Moderator
Moderator

Hi JeHu_3414236,

I changed the power mode to use 1.1V buck normally and 0.9V buck during deep sleep.  It seems to be working when I switch modes like this but I don't think it is correct:

Can you please let me know the core clock frequency? If it is greater than 50 MHz, then you will have to change the clock frequency as 0.9 V does not support frequency higher than 50 MHz. Also, there is a delay of around 200 us for the voltage change to take effect. Apart from this, it should be fine.

I tried to register a deep sleep callback handler and set buck voltage there but the current does not go down in deep sleep:

This might be because the BEFORE_TRANSITION is after Deep Sleep API enters the critical section and we need interrupts (for a syscall inside the API to return successfully) in the SetVoltage API.

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B
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JeHu_3414236
Contributor II

I am using FLL 48MHz.  Is this the core clock?  In the PSoC Creator Clock page, 48MHz is the highest clock setting for all clocks.

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RodolfoGL
Employee

You probably have CM4, Peripheral Clock and CM0+ running at 48 MHz.

Set the Peripheral Clock and CM0+ to run at 24 MHz, so you will be able to build the project.

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JeHu_3414236
Contributor II

I want to power off SRAM except for 64KB during deep sleep.  I am using dual-core PSoC62 with 288KB total SRAM.  Can you give me the code to do this?  Do I need to turn off/on every time I enter/exit deep sleep or only once at startup?

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RodolfoGL
Employee

Refer to this code example:

https://www.cypress.com/documentation/code-examples/ce226306-psoc-6-mcu-power-measurements?source=se...

This is the code to power down the RAM:

/* If in System Deep Sleep, check if SPEC ID requires to shutdown of SRAM */

/* Keep the first two pages enabled (64kB) */

#if (SPEC_ID == SIDDS1)

        for (uint32_t i = 2; i < NUM_RAM_PAGES; i++)

        {

            CPUSS->RAM0_PWR_MACRO_CTL = PWR_OFF_CTL_KEY;

        }

        CPUSS->RAM1_PWR_CTL = PWR_OFF_CTL_KEY;

        CPUSS->RAM2_PWR_CTL = PWR_OFF_CTL_KEY;

       

        /* Turn-off UDB Block */

        CPUSS->UDB_PWR_CTL = PWR_OFF_CTL_KEY;

#endif

You have to turn off/on every time you enter/exit deep sleep.

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JeHu_3414236
Contributor II

Thanks.  How do I turn on SRAM after exiting deep sleep?  The example only turns it off.

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RodolfoGL
Employee

Please refer to the PSoC 6 Register TRM. There is a register called CPUSS_RAM0_PWR_MACRO_CTL0.

The least significant bits tell which power mode to set:

Bits          Name                          Description

31 : 16      VECTKEYSTAT          Register key (to prevent accidental writes).

                                                    - Should be written with a 0x05fa key value for the write to take effect.

                                                    - Always reads as 0xfa05.

                                                    Default Value: 64005

1 : 0           PWR_MODE              Set Power mode for 1 SRAM0 Macro

                                                      Default Value: 3

                                                      0x0: OFF :

                                                      See CM4_PWR_CTL

                                                      0x1: RESERVED :

                                                      undefined

                                                      0x2: RETAINED :

                                                      See CM4_PWR_CTL

                                                      0x3: ENABLED :

                                                      See CM4_PWR_CTL

You can create another #define, like this:

#define PWR_ON_CTL_KEY     0x05fa0003

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