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PSoC 6 MCU

Contributor II

I am using J-Link to program the secure bootloader but the chip cannot reset and run the bootloader after programming is finished.  I have to cut the supply power and power on again for the bootloader to run.  If I connect a Miniprog 3 after programming, I can reset and run using PSoC Programmer by pressing the Load from Device button.  What is Miniprog 3 doing to reset and run that J-Link can't?  The device is powered by external voltage and not by the debugger.  This is the J-Link log when it is stuck:

Found SW-DP with ID 0x6BA02477

AP map detection skipped. Manually configured AP map found.

AP[0]: AHB-AP (IDR: Not set)

AP[1]: AHB-AP (IDR: Not set)

AP[2]: AHB-AP (IDR: Not set)

AP[1]: Core found

AP[1]: AHB-AP ROM base: 0xF0000000

CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)

Found Cortex-M0 r0p1, Little endian.

FPUnit: 4 code (BP) slots and 0 literal slots

CoreSight components:

ROMTbl[0] @ F0000000

ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table

ROMTbl[1] @ E00FF000

ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS

ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT

ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB

ROMTbl[0][1]: F0002000, CID: B105900D, PID: 000BB9A6 ???

ROMTbl[0][2]: F0003000, CID: B105900D, PID: 001BB932 MTB-M0+

Cortex-M0 identified.

J-Link>h

PC = FFFFFFFE, CycleCnt = 00000000

R0 = 08000830, R1 = 72707943, R2 = 00000000, R3 = 10000400

R4 = 000001A3, R5 = 00000D04, R6 = 16000200, R7 = 16000203

R8 = 7C230F57, R9 = 94A92521, R10= 49000A30, R11= 30E871C4

R12= 000000CA

SP(R13)= 080007F0, MSP= 080007F0, PSP= D00D2404, R14(LR) = FFFFFFF9

XPSR = 21000003: APSR = nzCvq, EPSR = 01000000, IPSR = 003 (HardFaultMemManage)

CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00

FPU regs: FPU not enabled / not implemented on connected CPU.

J-Link>r

Reset delay: 0 ms

Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

J-Link>h

PC = 00000F00, CycleCnt = 00000000

R0 = 00000000, R1 = 00000300, R2 = 05FA0000, R3 = 40210000

R4 = 16007C00, R5 = 00000D04, R6 = 16000200, R7 = 16000203

R8 = 7C230F57, R9 = 94A92521, R10= 49000A30, R11= 30E871C4

R12= 000000CA

SP(R13)= 08047800, MSP= 08047800, PSP= D00D2404, R14(LR) = 16002BAF

XPSR = 61000000: APSR = nZCvq, EPSR = 01000000, IPSR = 000 (NoException)

CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00

FPU regs: FPU not enabled / not implemented on connected CPU.

J-Link>go

J-Link>h

PC = 1000288E, CycleCnt = 00000000

R0 = 08000830, R1 = 72707943, R2 = 00000000, R3 = 10000400

R4 = 000001A3, R5 = 00000D04, R6 = 16000200, R7 = 16000203

R8 = 7C230F57, R9 = 94A92521, R10= 49000A30, R11= 30E871C4

R12= 000000CA

SP(R13)= 08000810, MSP= 08000810, PSP= D00D2404, R14(LR) = 10002889

XPSR = 21000000: APSR = nzCvq, EPSR = 01000000, IPSR = 000 (NoException)

CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00

FPU regs: FPU not enabled / not implemented on connected CPU.

CM4:

PC = 1600400C, CycleCnt = 87ED1EC5

R0 = 40210400, R1 = 0000000E, R2 = 402102C0, R3 = 16004000

R4 = 16004009, R5 = B5E02A00, R6 = 204C292E, R7 = 01B4BE8B

R8 = 39879D2D, R9 = 08026DFC, R10= 30ABB4F6, R11= AA668C14

R12= C1580459

SP(R13)= 00000000, MSP= 00000000, PSP= 8F3E240C, R14(LR) = FFFFFFFF

XPSR = 61000000: APSR = nZCvq, EPSR = 01000000, IPSR = 000 (NoException)

CFBP = 00000001, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 01

FPS0 = 8AC147BE, FPS1 = 31949889, FPS2 = 4617EC03, FPS3 = 8C422320

FPS4 = 940932AB, FPS5 = 704F86A2, FPS6 = DE7A2D60, FPS7 = A8E98CCB

FPS8 = 2C41A285, FPS9 = 0206A17A, FPS10= 2666A854, FPS11= 50D686C2

FPS12= A4B553C6, FPS13= ED1BD089, FPS14= 24B5E15A, FPS15= 0258DACC

FPS16= 0642280C, FPS17= CD070262, FPS18= 84AF188E, FPS19= 81152560

FPS20= 60B383C8, FPS21= CB69B1B0, FPS22= E381F182, FPS23= C7858285

FPS24= 8C8DC7F4, FPS25= 4AE2A08F, FPS26= 68A071EC, FPS27= 5C209461

FPS28= 6D42298A, FPS29= A3E07974, FPS30= 2A0050B1, FPS31= 04D18981

FPSCR= 00000000

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1 Solution
Employee

Just for the sake of understanding,  check if you have connected the Gnd of both the host programmer and target together?

If you see XRES pin functionality, from the picture given above, if the XRES pin of the target is given VSS potential, then reset takes place. 

If the connections are fine, can you short XRES of the target with the VSS(Target Gnd) just for a second to check if the reset works. If so, I don't think PSoC 62 has any issue with the reset functionality. You have to look at host programmer side for debugging this issue.

Thanks.

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5 Replies
Moderator
Moderator

In PSoC Programmer,  go to Options > Programmer Options. Here you will see that Auto Reset of Chip will be enabled. This is what causes the reset to occur in the case when you use a Miniprog3.

When using the J-Link, can you try the command "rnh" (Reset without halting the target) instead of "r" and check? Since you said, turning ON/OFF power supply works, can you try the command "power" and check if it works?

Let me know your observations.

Regards,

Dheeraj

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Contributor II

I tried rnh and power and they don't work.  Power is not supplied by J-link to the board.  It is external powered.

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Moderator
Moderator

Are the physical connections between the programmer and the debugger in accordance with this?

jtag2.PNG

More information on this can be found in Page#20 of the Programming Specfication​.

Regards,

Dheeraj

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Contributor II

Yes.  VDD on J-Link is connected to external 1.8V and not connected to anything on PSoC side.

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Employee

Just for the sake of understanding,  check if you have connected the Gnd of both the host programmer and target together?

If you see XRES pin functionality, from the picture given above, if the XRES pin of the target is given VSS potential, then reset takes place. 

If the connections are fine, can you short XRES of the target with the VSS(Target Gnd) just for a second to check if the reset works. If so, I don't think PSoC 62 has any issue with the reset functionality. You have to look at host programmer side for debugging this issue.

Thanks.

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