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PSoC 6 MCU

Contributor II

I am connecting VDDIO0 to 2.5V for e-fuse programming while the rest of the VDD voltages are 1.8V or 3.3V.  When the chip is powered off, all voltages are 0V but VDDIO0 will remain at 2.5V in some cases.  Will this design have any problems?

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Contributor II

I don't have the board any more.  It has been sent out for analysis.  I made a change to the board design so VDDIO0 is never high if the other supply voltages are low.

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Moderator
Moderator

The power rails for different pin ports are independent. You can power anyone of them regardless of the other rails' power state.

Any concern over this case?

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Contributor II

One custom board that was produced under this design draws very high current if 2.5V is supplied to VDDIO0 even with other supply voltages at 0V.  I cannot determine the cause but it seems like the PSoC 62 chip is damaged.

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Moderator
Moderator

I have not tested yet, but I don't think a single power supply to VDDIO0 can damage a whole chip. Can you verify the chip still be full-functioned?

Similarly, it works finely when only VBACKUP is on to run backup domain with powering port0 pins.

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Contributor II

I don't notice any change to functionality except for current greater than 200mA.  Capsense, SPI, UART, ADC, USB all function normally.  I don't have anything connected to ports 11 and 12 which use VDDIO0, however.

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Moderator
Moderator

200mA sounds a much high current. Possible to check if any leak current on your board? Does the current return back normal if you run the Capsense/SPI/UART... functionality instead of single VDDIO0 on?

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Contributor II

I don't have the board any more.  It has been sent out for analysis.  I made a change to the board design so VDDIO0 is never high if the other supply voltages are low.

View solution in original post

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