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PSoC 6 MCU

New Contributor

Hello,

I recently designed a PCB using CY8C6137BZI-F34 MCU, and it seems there is something somewhat unclear in the documentation.

I based my design on the recommendations in the "Design examples for unused SIMO VBUCK" thread (https://community.cypress.com/thread/46660​), which states that:

The SIMO pins VBUCK1, VRF, VDD_NS, VIN1 and VIND2 can be left floating. VCCD is Internal core regulators' (LDO) output. It requires bypass capacitor connection for proper operation. 1uF is connected on VCCD when VBUCK1 does not power VCCD.

I did exactly that in my design with a 1 µF capacitor on VCCD:

pastedImage_6.png

However, our firmware engineer had to choose the "Core Regulator" as "Buck" in the "System/MCU Parameters" section in Modus Toolbox, as shown below:

pastedImage_2.png

The other option "Normal Current LDO" is set in the CY8CKIT-062-WiFi-BT using CY8C6247BZI-D54 MCU:

pastedImage_10.png

This design has an inductor connected between VIND1 and VIND2 and pins VBUCK1 and VCCD connected together through R129:

pastedImage_7.png

This looks to be counter-intuitive, since the way I designed it would use the internal LDO, and the way the CY8C6247BZI-D54 was designed would use a buck regulator ... anyway, with "Buck" chosen as the Core Regulator, our design seems to work.

From the information I can gather in the "PSoC 6 MCU Hardware Design Considerations" document (AN218241) at section 3, there is an on-chip buck regulator that outputs a voltage on VBUCK1 pin, and we can choose to supply VCCD with it or not. Contrary to what the "Design examples for unused SIMO VBUCK" thread states, this pin should not be left floating and would require and bypass capacitor for proper operation (not present in our design). As for VCCD, it is the internal core regulator's output, and requires a bypass capacitor for proper operation (present in our design).

With that in mind, could someone please help me with the following questions?

- Is there something missing in my design that could cause problems later? I think that I might require a bypass capacitor on VBUCK1 pin.

- Do I have to connect VBUCK1 with VCCD, or can I leave it like that? Are there limitations in not connecting them?

- Are there any system configurations precautions that we should take in Modus Toolbox?

Thanks for your help!

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Moderator
Moderator

Hi,

Your queries will get cleared if yo refer the power system block diagram in page 129 of the device architecture TRM.

https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-61-architecture-te...

1. You can choose either Buck converter or LDO to supply power to your PSoC.

2. If you chose LDO you should leave the Buck power rails floating.

(Note under table 3 in PSoC 6 Hardware design considerations application note)

3. If you choose on chip buck converter to power your chip, then the VBUCK1 should be connected to VCCD and a decoupling capacitor of          4.7uF should be placed on the VBUCK1 pin. There is no need for any decoupling capacitor on the VCCD pin.

4. If you choose LDO to power your chip (dont use Buck) then there should be a single 1uF decoupling capacitor placed on the VCCD pin. In        this case VBUCK1 should not be connected to the VCCD pin.

    Please refer page number 33 of the PSoC 61 family datasheet.

    https://www.cypress.com/file/385931/download

Your schematic looks fine. You dont have to connect VBUCK1 to VCCD since you are using VDDD rail. There will not be any problems in future.

>>"Are there any system configurations precautions that we should take in Modus Toolbox?"

Cypress--> No need. If you see anywhere to fill the boxes with voltages, please fill with those voltages that you actually provide on the chip.

Please update if you have any queries.

Thanks

Ganesh

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1 Reply
Moderator
Moderator

Hi,

Your queries will get cleared if yo refer the power system block diagram in page 129 of the device architecture TRM.

https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-61-architecture-te...

1. You can choose either Buck converter or LDO to supply power to your PSoC.

2. If you chose LDO you should leave the Buck power rails floating.

(Note under table 3 in PSoC 6 Hardware design considerations application note)

3. If you choose on chip buck converter to power your chip, then the VBUCK1 should be connected to VCCD and a decoupling capacitor of          4.7uF should be placed on the VBUCK1 pin. There is no need for any decoupling capacitor on the VCCD pin.

4. If you choose LDO to power your chip (dont use Buck) then there should be a single 1uF decoupling capacitor placed on the VCCD pin. In        this case VBUCK1 should not be connected to the VCCD pin.

    Please refer page number 33 of the PSoC 61 family datasheet.

    https://www.cypress.com/file/385931/download

Your schematic looks fine. You dont have to connect VBUCK1 to VCCD since you are using VDDD rail. There will not be any problems in future.

>>"Are there any system configurations precautions that we should take in Modus Toolbox?"

Cypress--> No need. If you see anywhere to fill the boxes with voltages, please fill with those voltages that you actually provide on the chip.

Please update if you have any queries.

Thanks

Ganesh

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