Dear Cypress community,
my name is Julia and I'm studying medical engineering. For my master thesis project I'm developing a portable ecg system with PSoC 6 and ADS1298R.
I spent a few days trying to fix an issue with my SPI DMA and found no solution. I hope you can help me.
I'm trying to read out the ADS1298R FIFO using SPI + TX and RX DMA.
When new data of the ADS is ready the pin DRDY goes low and causes an interrupt (ECGInterruptIsr). Inside the ISR TX and RX DMA get enabled to start the transfer.
The problem is that the DMA transfer seems to work only every second data conversation. The SPI Done Interrupt (AFE_SPIM_IntHandler) is only triggered every 4 ms. But it should trigger every 2ms, because the sampling rate is set to 500 SPS. The timing diagram below shows the problem.
The SPI-Timing is right and follows this timing diagramm:
I configure the DMA components (RX and TX) to transfer 27 Bytes in one X-Loop. The attachement 1 shows all my configuration settings. Also The TX DMA transfer seems to work well but the RX transfer seems to transfer three bytes less than configured in the component editor.
This picture shows the false bytes. It should contain the Status Word. But the Status Word begins with the fourth byte.
This the timing digramm for one data conversation:
Im using the PSoC 6 BLE Pioneer Kit CY8CKIT-062-BLE
In the attachment you can see
Please let me know if you need more information.I am very grateful for any helpful response
Can you try reducing the bit rate and check if you still face this issue?
Looks like there were few elements in the RX FIFO that were not read during the previous transaction (0xDB 0xFB 0x46) and that this were read during the next transaction. Maybe that is why you see these 3 bytes of data and then your actual data.
Can you please provide a more clear waveform image of the transaction? (With clear markings of which is MISO, MOSI, CLK and SS)?
The SPI Done Interrupt (AFE_SPIM_IntHandler) is only triggered every 4 ms. But it should trigger every 2ms, because the sampling rate is set to 500 SPS. The timing diagram below shows the problem.
The SPI Done Interrupt is triggered whenever all the elements in the TX FIFO is transferred. I do not understand what you mean by "should trigger every 2 ms because data rate is 500 SPS"? Could you please provide more detail?
Can you please share your entire Creator project file (zipped version), so that I will try to reproduce your issue at my end?