Dear Cypress community,
I spent a few days trying to fix an issue with my SPI DMA and found no solution. I hope you can help me.
I'm trying to read out the ADXL372 FIFO using SPI + TX and RX DMA.
The FIFO watermark interrupt causes the TX and RX DMA to start the transfer (inside the ISR).
The TX DMA transfer works very well but the RX transfer seems to transfer one byte less than configured in the component editor.
I set up the accelerometer to trigger the watermark interrupt at 507 FIFO samples which means
that 169 Sample Sets ( 1 Set = 6 bytes x-y-z-Axis data = 1014 bytes + 1 Byte Opcode ) has to be transferred.
Due to the maximum transfer limit of 256 bytes, I decided to configure the DMA components (RX and TX) to transfer 203 Bytes in one X-Loop and
repeat this 5 times. In the RX DMA component, after each X-Loop the destination address is increased by 203 bytes.
An RX DMA complete interrupt should be triggered after the last X-Loop has been finished.
I have configured a GPIO Pin to go High when the DMA transfer is started and go low when the RX Finish interrupt is triggered.
Im using the PSoC 6 EZ BLE Module (CYBLE-416045-02 43-SMT)
In the attachment you can see
Please let me know if you need more information.
I am very grateful for any helpful response and wish everyone a happy new year.
From the "Debug View pics" I see that your RX buffer seem to have 1015 elements already (index 1015 is 1016th element). So I think Rx DMA might have transferred 1015 bytes and got disabled resulting in the missing byte. Now, the below are possible causes -
1. Rx DMA might have transferred one extra/invalid byte from the FIFO in middle somewhere - Since the initial data seemed to be in sync and the final data seemed to be out of sync tells this out-of-sync might have happened in middle
2. SPI might have transferred one additional byte again somewhere in the middle
I am not exactly sure what might be going wrong - can you attach the full Logic analyzer data for one full FIFO transfer to check what is going on on the MOSI and MISO? You can try changing the trigger to "16 Clk_Slow cycles" from "4 Clk_Slow cycles" - since SPI is anyway doing at 5 MHz rate (1.6 us per 8-bit transfer), it is ok to wait 320 ns before deciding the next trigger (instead of 80 ns). This will help in case, some rogue triggers were getting activated because of fast trigger rate.
Meenakshi Sundaram R
thanks for your response.
I have made the following test.
The data have been transferred via DMA and sent via BLE out to check if there is an out of sync issue without starting a debug session.
Each x-loop (203 bytes) was sent in a 203 byte notification (so 5 notifications for the whole FIFO transfer)
The pictures + Logic Analyzer Capture are showing that the data are in sync but the last byte is missing.
I have attached the logic analyzer data but you need the Saleae software to visualize them.