PSoC 6 MCU VDAC Sine Wave Generator Using DMA using CYBLE-416045-EVAL EZ-BLE cannot achieve 5kHz sine wave

[KyWe_1936431]

Hello,

I used the example code PSoC 6 MCU VDAC Sine Wave Generator Using DMA with the CYBLE-416045-EVAL EZ-BLE. It does create a sine wave, and I can control the frequency by controlling the clock divider with "Clock_1_SetDivider(Clk_Divide);" where Clk_divide is 16 or greater. However when Clk_divide is 16 the sine wave is supposed to be 5kHz but it is only around 3.8kHz. Oddly enough if the Clk_Divide is 19 the sine wave is higher frequency (around 4.2 kHz). Let me know if I need to clarify anything or add the code I used to cycle through frequencies.

Thank you,

Kyle Weeks

[SampathS_11]

Hello Kyle Weeks,

The peripheral clock is 50MHz. Clock_1 outputs 500kHz, hence the divider is set to 100. Kindly refer to the picture below:

This clock is further divided by 100, which is the number of sample points for the sine wave. Hence, we get an output of 5kHz. Kindly refer to the picture below:

Hence, to get 5kHz sinewave, the clock divider should be 100 for Clock_1 component.

If you are looking for a variable frequency output, you may want to explore Clock_1_SetFracDivider.

You can also refer to PSoC 6 Peripheral Driver Library Peripherals Clock Dividers

Best regards,

Sampath Selvaraj

[KyWe_1936431]

Hi Sampath Selvaraj,

The setfracdivider function looks useful. The peripheral clock I'm using is 8Mhz. I think its based on the internal main oscillator (IMO). Thats where the 16 divider comes in (8MHz/16 =500kHz). My main problem though is that the DAC is not updating at that rate. As the divider gets larger it becomes more accurate, but when the divider is 16 the frequency is not 5kHz.

I'm going to try changing the peri clock source to the FLL as I think yours is. I also want to see if the fractional divider works. I will get back to this after I've tried those things.

Thank you,

Kyle

[KyWe_1936431 · Accepted solution]

Some more detail about the problem when the input clock is the IMO, d is the divider, and f is the frequency of the sine in kHz

d=16 f=3.16

d=17 f=3.58

d=18 f=4.24

d=19 f=4.0

I tried using Clock_1_SetFracDivider() and for some reason it wouldn't allow me to update every couple seconds like I can with Clock_1_SetDivider(). I went to top design and checked the box to allow fractional divides and now it works. I Also tried using the FLL clock to run the peripheral clock. The FLL is 25MHz and with a 50 divider I can get up to 4.9 kHz which is much better.

Also a side note; I accidentally set up clock1 to be faster than 500kHz and the program still worked. Will going faster than the recommended 500kHz damage the DAC?

Thank you,

Kyle

[SampathS_11]

Hello Kyle,

It may not damage the DAC if a faster clock is applied for a few moments. It is best to follow the recommended specifications.

Thanks, and regards,

Sampath Selvaraj