PSoC 6 I2C Master with slave using clock streching

[Mykee]

I'm using a CY8C6137 PSoC 6 connected via I2C to a device using clock stretching. The PSoC 6 is the master and the device the slave. Clock stretching is done between the data and the acknowledge.

When the device transmits it holds the SCL line low after the 8th bit while it prepares the next byte, releases the SCL line and then reads the ACK bit from the PSoC 6. When the device receives, it holds the SCL line low after it receives the 8th bit then sends ACK or NACK.

How is I2C clock stretching handled in the PSoC 6? It's no problem if basic APIs need to be modified as I already have done so for other purposes.

[Alakananda_BG]

Hi @Mykee ,

Clock stretching is handled in hardware and it is enabled by default, no api modification is required.

Regards

[Mykee]

Hi Alakananda,

Just to be clear that the hardware handles the cases below. Can you confirm. Thanks.

1. PSoC master transmits to slave which does clock stretching between data and ack.

This case is straightforward as the PSoC 6 just needs to wait for the ack clock signal from the slave.

2. PSoC master transmits to slave which does clock stretching after ack.

In this case, if there are bytes in the transmit FIFO, the hardware would need to verify that the SCL line is released by the slave (going high) before starting transmission of next byte.

3. PSoC master receives from slave which does clock stretching between data and ack.

If auto ack is enabled, the PSoC would have to verify that the SCL line is released by the slave (going high) before sending ack. If ack is sent manually, such as in the function Cy_SCB_I2C_MasterReadByte, the PSoC would have to wait for the SCL line to be released before executing the ack command.

3. PSoC master receives from slave which does clock stretching between after ack.

Straightforward as the PSoC 6 just needs to wait for the next data.

Preview

[Alakananda_BG · Accepted solution]

Hi,

1. PSoC master transmits to slave which does clock stretching between data and ack.

-> This is true. The master will wait to receive an ack signal from the slave since the SCL line is pulled low by the slave.

2. PSoC master transmits to slave which does clock stretching after ack.

-> This condition is not clear. After the slave sends an ack condition, the slave should not control the SCL line. It should leave both SDA and SCL line after it has sent an ACK. After a ACK is received, the master will proceed towards sending the next byte if there is some data in the TX FIFO. ie Clock stretching is not performed after the slave has sent an ACK.

3. PSoC master receives from slave which does clock stretching between data and ack.

-> When the master is receiving data from the slave, slave has no control over the SCL lines. Clock stretching is not performed in this case. If auto ack is enabled, the master will immediately send out the ACK as soon as it receives 8 bits from the slave . Clock stretching is not allowed since slave does not control the SCL line during this phase.

4. PSoC master receives from slave which does clock stretching between after ack.

-> There is no such condition. Slave does not control SCL line when sending data to the master. Therefore clock stretching is not performed.

Regards