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PSoC 6 MCU

ChRe_4711096
New Contributor II

We're working on a project that requires 5 or 6 hardware counters. Using Count7 works well, but we only need 3 bits of those counters and we're running out of UDBs for other tasks.

So: is it possible to implement 2 3-bit counters using just one UDB? That would be quite a relief. We'd need (roughly) the following API:

- initialize and enable

- set period

- read and write current counter value

The component would have two clock inputs and two cnt[2:0] outputs. A tc output is not necessary.

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1 Solution
RodolfoGL
Employee

Your bottle neck is the Control Cells, which implements the Control Registers and Count7 cells.

The component I attached previously might be helpful then.

View solution in original post

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11 Replies
NoriakiT_91
Employee

There are two 8-bit accumulators A0 and A1.

If it is not required to increment both counters at once, two 8-bit counter will be implemented in one UDB.

Just an idea.

Regards,

Noriaki

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MotooTanaka
Esteemed Contributor

Hi,

I just tried for fun.

(I have not tested it, so please take it as just a sample)

In my implementation,

if we1 is high max1 is written to the cnt1. or cnt1 counts 0 to max1 when en1 is high and at the posedge of clk1

same for 2.

rst resets both counters to 0.

The ResourceMeter showed below, I wonder if this is less than a UDB or not.

002-resource.JPG

schematic

001-schematic.JPG

verilog HDL (counter3x2.v)

==================

//`#start header` -- edit after this line, do not edit this line

// ========================================

//

// Copyright YOUR COMPANY, THE YEAR

// All Rights Reserved

// UNPUBLISHED, LICENSED SOFTWARE.

//

// CONFIDENTIAL AND PROPRIETARY INFORMATION

// WHICH IS THE PROPERTY OF your company.

//

// ========================================

`include "cypress.v"

//`#end` -- edit above this line, do not edit this line

//`#start body` -- edit after this line, do not edit this line

module counter3x2(

    input rst,

    input clk1,

    input we1,

    input en1,

    input [2:0] max1,

    input clk2,

    input we2,

    input en2,

    input [2:0] max2,

    output reg [2:0] cnt1,

    output reg [2:0] cnt2

    ) ;

      

    counter3 inst1 (rst, clk1, we1, en1, max1, cnt1) ;

    counter3 inst2 (rst, clk2, we2, en2, max2, cnt2) ;

  

endmodule

module counter3(

    input rst,

    input clk,

    input we,

    input en,

    input max,

    output reg [2:0] cnt

    ) ;

  

    always @ (posedge rst or posedge clk) begin

        if (rst == 1'b1) begin

            cnt <= 3'd0 ;

        end else begin

            if (we == 1'b1) begin

                    cnt <= max ;

            end else begin

                if (en == 1'b1) begin

                    if (cnt >= max) begin

                        cnt <= 3'd0 ;

                    end else begin

                        cnt <= cnt + 3'd1 ;

                    end

                end

            end

        end

    end

endmodule

//`#end` -- edit above this line, do not edit this line

//`#start footer` -- edit after this line, do not edit this line

//`#end` -- edit above this line, do not edit this line

//[] END OF FILE

==================

moto

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ChRe_4711096
New Contributor II

Thank you, this looks like a good start - I guess what you see in the Resource Meter is that the counting is implemented with P-Terms, and since you have inputs for the period values and only hardware outputs for the current counter value, no status and control registers are used. When an API is added (set period, set counter, get counter), the implementation would use one status and one control register for each pair of counters.

I'll give it a try and see if I'm able to add an API.

ChRe_4711096
New Contributor II

Another thought: it will probably be hard (or impossible, I don't know) to use each half of this double-counter individually as sub-components to another component, especially when it comes to the API.

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MotooTanaka
Esteemed Contributor

Hi,

Although I'm not sure if I understand your question correctly, one reason I did not attach "ControlReg" or "StatusReg" to my first sample was to make it possible to connect the component pins to other components' pins so that it can be used as a sub module of that component or circuit.

moto

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RodolfoGL
Employee

I think you can implement 4 8-bit counters with one UDB.

The idea is to store in the internal FIFO the current counter. Since the FIFO has 4 elements, we can have up to 4 counters.

A few questions:

1) Do you need to run the counters with a different frequency?

2) What are the inputs and outputs? Same as the 7-bit counter?

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ChRe_4711096
New Contributor II

Maybe it helps to have a look at the overall task (build a 4in1 BLDC motor controller).

Here's my top level design. It contains 4 ESC_Comm components on the right:

topDesign.png

The ESC_Comm components need a 3-bit counter each (in the center). As it is now, it occupies 2 Control Registers (one for ESC_Ctrl and one for Count7):

ESC_Comm.png

It's possible to remove 1 bit from ESC_Ctrl, so I'd have 4 bits in that Ctrl Reg left to make an API for the 3-bit counter. Since I'd need to set the counter in the code for the ESC_Comm component, those 4 bits could be the counter value and a write enable bit. An nable input to the counter isn't strictly necessary, I can simply stop Timer_Comm to make the counter not count.

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RodolfoGL
Employee

That's a very impressive design with the UDBs.

What I proposed before would require to combine all the ESC_Comm_X components, so you could share the counter. Or create a new input in the ESC_Comm for the counter lines.

Perhaps there is a better way. Can you share your *.RPT file (it reports how you are using the hardware resources). If you have a few datapath left, we can implement a datapath counter instead.

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RodolfoGL
Employee

I'm attaching the simplest Datapath Counter you can get. It doesn't consume any PTerms or Microcells.

If using the CY8CKIT-062-WIFI-BT, press the Kit's button and observe the LEDs blinking.

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ChRe_4711096
New Contributor II

Here it is - no datapaths in use, so we could well target those. The ESC_Comm components currently occupy 8 UDBs. Combining their Count7 and Control Reg into one UDB would be a huge step forward. I just don't have any prior experience with the UDBs (or PSoC in general tbh) so I couldn't really tackle that yet.

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RodolfoGL
Employee

Your bottle neck is the Control Cells, which implements the Control Registers and Count7 cells.

The component I attached previously might be helpful then.

View solution in original post

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