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PSoC 6 MCU

MuKh_4408861
New Contributor II

Hi All,

I've designed PCB with CY8C6347FMI-BLD53T in 104-WLCSP package.

It turned out that our current PCB manufacturer cannot make this PCB because of too small clearance min = 2mil.

I'm using 0.1mm hole Vias between pads to wire out processor signals, but they complain on that too.

What is optimal via size for this footprint wiring?
Is there any guide for this package PCB design?

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1 Solution
Hari
Moderator
Moderator

Hi MuKh_4408861​,

The layout design has to use a micro via and it has to be on pad. You can set constraints by referring IPC standards and their PCB manufacturer spec.

This design needs PCB manufacturer capable of supporting laser drilled vias and stacked vias.


Thanks,

Hari

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4 Replies
Hari
Moderator
Moderator

Hi MuKh_4408861

The CY8C6347FMI-BLD53 ​ part is not 104-WLCSP but 104-MCSP package. You can check the  PSoC 6 cad library ​for details on the package. You can see that each pin is 7 mil in width and there is 13 mil spacing between each pin. 7 mil is standard PCB process and your manufacturer would be able to provide this.

We do not have a reference PCB for 104-MCSP package.

Thanks,
Hari

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MuKh_4408861
New Contributor II

Thanks for reply.
Apparently there is typo in Datasheet page 73. The footprint named as "104-WLCSP 3.8 × 5.0 × 0.65 mm".

But, in other places it named correctly - MCSP.
Part coding is also correct
CY8C6347FMI-BLD53 FM for M-CSP and FN for WLCSP.

I was using third party footprint, which is not the best idea. Hopefully after footprint update PCB manufacturers will not complain.

"7 mil is standard PCB process" If you use Vias between pads it is impossible to achieve 7 mil clearance. Otherwise you have to use via-in-pad technique. But this method is not very common and consist other risks. Like Via fills need to be very flush with surface.

PS. Life would be much easier if there was some reference/link from DS or from part web page
to  PSoC 6 cad library .
Thanks again for help.

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MuKh_4408861
New Contributor II

I'm sorry but after all this does not work. Manufacturer cannot make even with Cypress library part.
Your mentioned "pin is 7 mil in width and there is 13 mil spacing" is correct, but to wire out internal pins you need to use Vias. This makes things much worse than that. The only way to do that with "standard" PCB manufacturer capabilities is to make via-in-pad.

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Hari
Moderator
Moderator

Hi MuKh_4408861​,

The layout design has to use a micro via and it has to be on pad. You can set constraints by referring IPC standards and their PCB manufacturer spec.

This design needs PCB manufacturer capable of supporting laser drilled vias and stacked vias.


Thanks,

Hari

View solution in original post

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