I'm trying to understand how to determine the core that is currently being compiled while defining the proper macros for each core. I can see from the device header file with something like:
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
to determine which core header file to include (e.g., core_cm0plus.h or core_cm4.h).
Since I'm using ARMCC, is there any way to understand how __TARGET_ARCH_THUMB is defined to know which core the PSoC Creator is currently compiling?
Solved! Go to Solution.
I created an example project with two interrupts for M0 and M4 as follows.
And confirmed the generated source "cyfitter_sysint_cfg.h" at the interrupt configuration.
/* ARM CM0+ */
#if (((__CORTEX_M == 0) && (CY_CORE_ID == 0)))
#define SysInt_M0__INTC_ASSIGNED 1u
extern const cy_stc_sysint_t SysInt_M0_cfg;
#endif /* ((__CORTEX_M == 0) && (CY_CORE_ID == 0)) */
/* ARM CM4 */
#if (((__CORTEX_M == 4) && (CY_CORE_ID == 0)))
#define SysInt_M4__INTC_ASSIGNED 1u
extern const cy_stc_sysint_t SysInt_M4_cfg;
#endif /* ((__CORTEX_M == 4) && (CY_CORE_ID == 0)) */
It seems that the __CORTEX_M macro is used to specify the current core.
I don't know what is the CY_CORE_ID indicating.
Thanks for the response. Yes I can understand that __CORTEX_M is defined and it is defined in either core_cm0plus.h or core_cm4.h. But however, I would still like to know how it is included in device header file under the #if statement mentioned previously. Specifically, how (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) is defined in the source code.