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PSoC 6 MCU

MiZu_4805356
New Contributor II

Hello.

I am using CY8C624A (PSoC 62 - 2 MiB Flash). According to cyip_gpio_v2.h file as part of PSoC 6 PDL at Github​ there are some CFG_SIO register with offset 0x50 to the base address of GPIO port configuration. But it is not documented in Register TRM. The last described register of PRT0 is GPIO_PRT0_CFG_OUT at 0x4031004C and next one is first register of PRT1 at 0x40310080. There are no description for register at 0x40310050. Why is this register ommited in Register TRM? What is it used for?

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Thank you.

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1 Solution
VenkataD_41
Moderator
Moderator

Hi,

SIO is not present in any PSoC 6 devices – hence Register TRM does not talk about it.

Since it is a feature that may come in future (not yet decided by Cypress), PDL already reserves param for that.

Hope this clears your query.

Thanks

Ganesh

View solution in original post

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VenkataD_41
Moderator
Moderator

Hi,

SIO is not present in any PSoC 6 devices – hence Register TRM does not talk about it.

Since it is a feature that may come in future (not yet decided by Cypress), PDL already reserves param for that.

Hope this clears your query.

Thanks

Ganesh

View solution in original post

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