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PSoC 6 MCU

lozhc_4109776
New Contributor

I'm trying to incorporate the example from the eeprom example:

CE195313 PSoC Emulated EEPROM

into my project.

However when I build the project, an error occured, If anyone could help me that would be great! Thanks!

Here's my eeprom configuration:

EEPROM Size: 8192

Redundant Copy: No

Use Blocking Write: No

Use Emulated EEPROM: Yes

Wear Level Factor: None

EEPROM configuration in ld files both of CM0 & CM4:

em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */

And my error log:

No ELF section .cychecksum found, creating one

Application checksum calculated and stored in ELF section .cychecksum

Checksum calculated and stored in ELF section .cymeta

"C:\Program Files (x86)\Cypress\PDL\3.0.4\tools\win\elf\cymcuelftool.exe" --merge C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM4\ARM_GCC_541\Debug\BLE_KEY_signed.elf C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM0p\ARM_GCC_541\Debug\BLE_KEY.elf --output C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM4\ARM_GCC_541\Debug\BLE_KEY.elf --hex C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM4\ARM_GCC_541\Debug\BLE_KEY.hex

C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM0p\ARM_GCC_541\Debug\BLE_KEY.elf: Merge error: Section 0x14000000 at C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM0p\ARM_GCC_541\Debug\BLE_KEY.elf overlaps section 0x14000000 from C:\Users\XuRi\work\CYPRESS\BroJiaXing\f0v3EEPROM\f0v3\BLE_KEY.cydsn\CortexM4\ARM_GCC_541\Debug\BLE_KEY_signed.elf,

but it contains different data

The command 'C:\Program Files (x86)\Cypress\PDL\3.0.4\tools\win\elf\cymcuelftool.exe' failed with exit code '1'.

--------------- Rebuild Failed: 03/18/2019 14:28:27 ---------------

1 Solution
ShipingW_81
Moderator
Moderator

It looks from the error log that you introduce both BLE and EEPROM components in your project. The building error is just because

there is a working-flash region allocated for BLE to store the Bonding list, and this region always only be allocated for the core where BLE host lies. It means a kind of out-sync for the two cores.

You can adjust the allocation of working-flash for cores according to your actual application requirements.

I. allocate Working-flash memory for only one core

Here assume only cm4 accesses to working flash, linker file of cm0+ (cy8c6xx7_cm0plus.ld) should be modified as below.

comment below line:

em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000

or

comment below code snippet:

/* Emulated EEPROM Flash area */

.cy_em_eeprom :

{

KEEP(*(.cy_em_eeprom))

} > em_eeprom

II. Split working flash space for two cores respectively

This should be implemented by modifying linker files for two cores. e.g. as below:

cy8c6xx7_cm0plus.ld:

em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x4000

cy8c6xx7_cm4_dual.ld:

em_eeprom (rx) : ORIGIN = 0x14004000, LENGTH = 0x4000

Let me know if the above methods meets your requirements.

View solution in original post

3 Replies
ShipingW_81
Moderator
Moderator

It looks from the error log that you introduce both BLE and EEPROM components in your project. The building error is just because

there is a working-flash region allocated for BLE to store the Bonding list, and this region always only be allocated for the core where BLE host lies. It means a kind of out-sync for the two cores.

You can adjust the allocation of working-flash for cores according to your actual application requirements.

I. allocate Working-flash memory for only one core

Here assume only cm4 accesses to working flash, linker file of cm0+ (cy8c6xx7_cm0plus.ld) should be modified as below.

comment below line:

em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000

or

comment below code snippet:

/* Emulated EEPROM Flash area */

.cy_em_eeprom :

{

KEEP(*(.cy_em_eeprom))

} > em_eeprom

II. Split working flash space for two cores respectively

This should be implemented by modifying linker files for two cores. e.g. as below:

cy8c6xx7_cm0plus.ld:

em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x4000

cy8c6xx7_cm4_dual.ld:

em_eeprom (rx) : ORIGIN = 0x14004000, LENGTH = 0x4000

Let me know if the above methods meets your requirements.

View solution in original post

lozhc_4109776
New Contributor

Thank you for your answer, things have changed.

The second way of "allocate Working-flash memory for only one core" is effective.

After modify code according to this way like below, my project build successfully.

/* Emulated EEPROM Flash area */

.cy_em_eeprom :

{

KEEP(*(.cy_em_eeprom))

} > em_eeprom

Unfortunately, other methods still cause compilation errors, and I don't know why.

I want to know what is the difference between choosing Use Emulated EEPROM option or not.

Could you tell me what is Emulated EEPROM really?

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ShipingW_81
Moderator
Moderator

For PSoC6, there is flash-emulated EEPROM, which occupies a dedicated flash section(0x14000000 – 0x14008000). The PDL provides specific Middleware/APIs to facilitate storing some custom data in EEPROM.

I did not figure out which method effective on your side, which one not.

The failed one, can you attach your error log?

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