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PSoC 6 MCU

efor
New Contributor

Hello all,

I am currently using a psoc CY8C6347BZI-BLD53 to do some very high speed SPI transfers at 25MHz and have come across some interesting behavior of the SPI FIFO. 

Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8. Upon further investigation with an oscilloscope there was some delay between transfers  (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.

The delay between each message becomes one clock cycle consistently when using Cy_SCB_WriteTxFifo() even while writing to the FIFO which solves my timing critical problem. However, I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38) . I found that if I add a delay of ~20 cycles after each call of Cy_SCB_WriteTxFifo() the right number of data (54) can be seen transferring on the oscilloscope before the next interrupt occurs.

I am reaching out for some help with trying to eliminate the added delay cycles after each Cy_SCB_WriteTxFifo, or at least to understand the root cause of why it work when they're there. I have looked into the TRM for the architecture, but they do not go into detail about FIFO operation. I don't have a usb right now so I can't post images from my oscilloscope but if you need them to understand I should have one by this Monday.

Your help is greatly appreciated!

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1 Solution
efor
New Contributor

Hello again Aashita,

To answer your questions, it was a master fifo level interrupt on tx low for a halfword to halfword transfer. After much testing I realized the cause of my issue was in clearing the interrupt too soon. When in the interrupt handler I first cleared the interrupt source and then began to fill the fifo, causing the continuous interrupts. The delayed message sending was probably caused because it could only put 1 more value into the fifo before the interrupt happened again. So my remaining question is:

Is there a more detailed documentation for the operations of the fifo? 

Thanks

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Aashita_Raj
Moderator
Moderator

Hi @efor ,

Can you please answer the below queries in order for me to understand your issue properly-

-> Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8.

Are you using Level Interrupt here?

-> Upon further investigation with an oscilloscope there was some delay between transfers (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.

Is this the case of byte to byte transfer?

-> I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38)

Can you please explain which interrupt are you talking about here?

Also, can you please attach your project  and let us know if your project is programmed for master or slave?

Please let us know about your comments about the above queries so that we can help you further.

Best Regards,

Aashita

 

 

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efor
New Contributor

Hello again Aashita,

To answer your questions, it was a master fifo level interrupt on tx low for a halfword to halfword transfer. After much testing I realized the cause of my issue was in clearing the interrupt too soon. When in the interrupt handler I first cleared the interrupt source and then began to fill the fifo, causing the continuous interrupts. The delayed message sending was probably caused because it could only put 1 more value into the fifo before the interrupt happened again. So my remaining question is:

Is there a more detailed documentation for the operations of the fifo? 

Thanks

View solution in original post

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Aashita_Raj
Moderator
Moderator

Hi @efor ,

Glad to know that you could find out the solution for your issue, after debugging. 

Also, Regarding your query about detailed documentation for operations of the FIFO, the architecture TRM for your device is the only source which you can refer to understand the operations of FIFOs. Please refer to section 26.6.1 of architecture TRM of PSoC 63 device here : https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architectur... 

Best Regards,

Aashita

 

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