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I am migrating a project which uses capsense to the PSoC6. Previously the 4100S was used to do touch sensing on three buttons; it worked well. Now, nothing related to capsense works. I have isolated the problem by using CE222827 - PSoC 6 MCU: Capsense Tuner with the capsense device using a single CSD button.
PDL 3.1.0 is being used. I am aware of the
Beware of automatic updating your project PDL components to the latest.
posting but have not been able to resolve the problem using the suggestions.
The project compiles and the capsense tuner is connected to 063-BLE via a UART. The data coming into the tuner is a constant 4095. Not even any noise shows.
The single touch sensor is connected to P7.1 and there is an external 0.47pF capacitor connected to it and ground.
Any suggestions as to what I could be missing?
Solved! Go to Solution.
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- cy8cproto-063-ble
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Hi,
Thanks for the project.
Although I don't have the hardware, I just tried to take a look at.
[Short Report]
(1) I could not build your project
(2) By doing "Update Components" to the project, I could build the project.
[Long Report]
So to see what's going on, I duplicated your projec to "UART02_Copy_01"
And I tried to "Clean and Rebuild" the project
Then I received the following dialogs
(Info) answered "OK"
Update Configuration Files
Checked all and selected "Replace"
Compile failed with an Error "cy_stc_system_callback_param_t ..."
Then I tried "Update Components..."
A dialog informing about unsaved documents, answered "Yes".
The "Component Update Tool" Dialog showed up.
There "CapSense" was included!
Selecting "Next > "
The update targets were CapSense (and LIN_Dynamic, which I don't care now)
Selecting "Finish"
To protect current project, Workspace/Project Archiver showed up.
Selected "Archive"
One more dialog, answered "Yes"
Summary for the archive
Then the folder containing the archive opened, but I just closed this.
Now the components (must be) up to date.
So I selected "Clean and Rebuild"
The project was build OK, this time.
Please try with this result, and let us know if you see any improvement.
moto
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Hi,
In the CY8CPROTO-063-BLE PSoC 6 BLE Prototyping Board Guide,
There are following descriptions.
I think that P7[1] is used for LED4, so can't you try with other GPIO pins?
Such as P7[2], P10[6] .. P10[0], P5[6]..P5[2], etc.
moto
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Sorry, for the test, the pin number used IS P7.2 and the capacitance is 0.47 nF. In the project we are using P7.1 also, but the red LED was removed from the board. The third sensor is on P9.5. The same results appear in the tuner for these other two pins so I reduced the test to just one pin. It would be great if just that would work.
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Hi,
Since you are using CSD, 0.47nF at P7.2 is not required.
So how about trying either
(1) Try using P7.1 (without LED) or other pins stated only as GPIO?
(2) Remove 0.47nF and use P7.2.
As I don't have the same board to test, I can not test it.
but if you can attach your project (cleaned and archived) with your response
it will help others to test it with their hardware(s).
moto
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I found that there may be an issue with the PDL version used. For my main application project, PDL 3.1.0 is used and everything is working fine except for the capsense.
When I tried to compile the capsense example, PDL 3.1.0 produced a compile error. When the PDL was switched back to 3.0.4 it compiled OK and started running. But the tuner has no data except constant 4095 values. The attached project bundle is using 3.0.4.
The project is using P7.2 and now the capacitor is removed.
I am not sure how to attache the project bundle so am using the "insert image".
Sorry, that did not work. The file was a little over 10MB so it was not accepted.
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Hi,
> I am not sure how to attache the project bundle so am using the "insert image".
> Sorry, that did not work. The file was a little over 10MB so it was not accepted.
Usually, I do
(1) set the target project as active project
(2) right-click the active project and from the pop-up menu select "Clean <project>"
(3) Again right-click the project and select "Archive Workspace/Project..."
(4) A couple of dialog windows will appear
The first one to specify the destination and the size
Please select "Minimal" to make the package small.
Then archive result summary will be shown, select [OK]
(5) The folder containing the archive will be opened, you need to attach the ".zip" file.
(6) Now to attach, at your response window, at first we do not have "attache" button.
So please select "use advanced editor" in the right - top corner.
(7) Then "attach" appears at the right-bottom corner.
Please use this to attach your ".zip" file.
moto
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Hi,
Thanks for the project.
Although I don't have the hardware, I just tried to take a look at.
[Short Report]
(1) I could not build your project
(2) By doing "Update Components" to the project, I could build the project.
[Long Report]
So to see what's going on, I duplicated your projec to "UART02_Copy_01"
And I tried to "Clean and Rebuild" the project
Then I received the following dialogs
(Info) answered "OK"
Update Configuration Files
Checked all and selected "Replace"
Compile failed with an Error "cy_stc_system_callback_param_t ..."
Then I tried "Update Components..."
A dialog informing about unsaved documents, answered "Yes".
The "Component Update Tool" Dialog showed up.
There "CapSense" was included!
Selecting "Next > "
The update targets were CapSense (and LIN_Dynamic, which I don't care now)
Selecting "Finish"
To protect current project, Workspace/Project Archiver showed up.
Selected "Archive"
One more dialog, answered "Yes"
Summary for the archive
Then the folder containing the archive opened, but I just closed this.
Now the components (must be) up to date.
So I selected "Clean and Rebuild"
The project was build OK, this time.
Please try with this result, and let us know if you see any improvement.
moto
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Hi StNu_1610991
As MoTa_728816 suggested, please update the component to the latest version (V3.0) to ensure compatibility with latest PDL. Apart from that a few suggestions regarding CapSense:
1. Please set the modulator clock frequency to the max possible (48MHz) (CapSense configurator > Advanced > CSD Settings > Modulator clock frequency). This will ensure faster scan time and will allow you to set higher sense clock speed.
2. Set the sense clock frequency to a higher value (CapSense configurator > Advanced > widget details > Sense clock frequency). The idea is to set the sense clock frequency to the maximum possible that charges and discharges the sensors completely. Setting a low value would mean the IDAC is also set to a low value and the error in IDAC might cause this issue. You can set the highest frequency and check if the sensors are charged and discharged in an oscilloscope (you will see square waves). If the sensors are being charged and discharged, you can keep it, else you can reduce the frequency.
Additionally, please make sure that a 2.2 NF capacitor is placed in pin 7.7 for Cmod. This is essential for CapSense operation.
You can also check the sensor lines with an oscilloscope to make sure that CapSense scan is happening (you will see square waves in those lines).
Thanks,
Hari
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Thank you for the reply. The problem was that the capsense component had not bee updated to the right version. After upgrading it sensor data did come in properly. I added the two other buttons on P7.1 and P9.5 as needed for the project; they were also being sensed properly.
Thanks for your help.