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PSoC 6 MCU

KoMa_4822621
New Contributor

I have successfully programmed and unprogrammed PSoC demos on the CY8CPROTO-062-4343W boards but once I program an aws_demo the board is bricked. The board runs the firmware but cannot be reprogrammed. I have tried this on 3 different boards with the same results. This thread discussed the same problem without providing a solution. BTW I have updated the adapter firmware tried the Cypress programmer as well.

Any help will be appreciated since I have had to order 3 new boards.

Log of errors

Open On-Chip Debugger 0.10.0+dev-4.1.0.1058 (2020-08-11-03:45)

Licensed under GNU GPL v2

For bug reports, read

  http://openocd.org/doc/doxygen/bugs.html

Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.

adapter speed: 2000 kHz

adapter srst delay: 25

adapter srst pulse_width: 25

** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable

cortex_m reset_config sysresetreq

cortex_m reset_config sysresetreq

Info : Using CMSIS loader 'CY8C6xxA_SMIF' for bank 'psoc6_smif0_cm0' (footprint 14672 bytes)

Warn : SFlash programming allowed for regions: USER, TOC, KEY

Info : CMSIS-DAP: SWD  Supported

Info : CMSIS-DAP: FW Version = 2.0.0

Info : CMSIS-DAP: Interface Initialised (SWD)

Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1

Info : CMSIS-DAP: Interface ready

Info : KitProg3: FW version: 2.10.878

Info : KitProg3: Pipelined transfers enabled

Info : VTarget = 3.325 V

Info : kitprog3: acquiring the device...

Error: kitprog3: failed to acquire the device

Info : clock speed 2000 kHz

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Polling target psoc6.cpu.cm0 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Examination failed, GDB will be halted. Polling again in 100ms

Error: Failed to read memory at 0xe000ed00

Polling target psoc6.cpu.cm0 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Examination failed, GDB will be halted. Polling again in 300ms

Info : starting gdb server for psoc6.cpu.cm0 on 3333

Info : Listening on port 3333 for gdb connections

Info : starting gdb server for psoc6.cpu.cm4 on 3334

Info : Listening on port 3334 for gdb connections

***************************************

Info : SWD DPIDR 0x6ba02477

** Device is not present in the UDD

Error: Failed to read memory at 0x16000000

Error: mem2array: Read @ 0x16000000, w=4, cnt=1, failed

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x16002004

Error: mem2array: Read @ 0x16002004, w=4, cnt=1, failed

Error: Invalid FlashBoot: High version word of Flash Boot is zero

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x402020c4

Error: mem2array: Read @ 0x402020c4, w=4, cnt=1, failed

Error executing event examine-end on target psoc6.cpu.cm0:

/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/mem_helper.tcl:6: Error:

in procedure 'program'

in procedure 'ocd_process_reset'

in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279

in procedure 'cy_get_set_device_param' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 129

in procedure 'show_chip_protection' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/cy_get_set_device_param.cfg", line 164

in procedure 'mrw' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/cy_get_set_device_param.cfg", line 118

at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/mem_helper.tcl", line 6

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Info : AP write error, reset will not halt

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

in procedure 'program'

Info : SWD DPIDR 0x6ba02477

Polling target psoc6.cpu.cm4 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Examination failed, GDB will be halted. Polling again in 100ms

** Program operation failed **

srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst

Polling target psoc6.cpu.cm0 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Examination failed, GDB will be halted. Polling again in 700ms

***************************************

Info : SWD DPIDR 0x6ba02477

** Device is not present in the UDD

Error: Failed to read memory at 0x16000000

Error: mem2array: Read @ 0x16000000, w=4, cnt=1, failed

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x16002004

Error: mem2array: Read @ 0x16002004, w=4, cnt=1, failed

Error: Invalid FlashBoot: High version word of Flash Boot is zero

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x402020c4

Error: mem2array: Read @ 0x402020c4, w=4, cnt=1, failed

Error executing event examine-end on target psoc6.cpu.cm0:

/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/mem_helper.tcl:6: Error:

in procedure 'ocd_process_reset'

in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 279

in procedure 'cy_get_set_device_param' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/psoc6_common.cfg", line 129

in procedure 'show_chip_protection' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/cy_get_set_device_param.cfg", line 164

in procedure 'mrw' called at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/target/mxs40/cy_get_set_device_param.cfg", line 118

at file "/Applications/ModusToolbox/tools_2.2/openocd/bin/../scripts/mem_helper.tcl", line 6

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: DP initialisation failed

Info : psoc6.dap: powering down debug domain...

Warn : Failed to power down Debug Domains

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1 Solution
RodolfoGL
Employee

Hi Kobus,

We confirmed that the amazon-freertos 201910-MTBAFR1951 is setting some internal bits in the SFlash incorrectly, causing the issue you observed.

The newest release, amazon-freertos 202007-MTBAFR41 fixed this issue.

Here is the list of releases:

Tags · cypresssemiconductorco/amazon-freertos · GitHub

We are still working on a method to recover the boards flashed with the old version. If we find a way to do so, we will post here.

View solution in original post

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27 Replies
Rakshith
Moderator
Moderator

Hi koma_4822621​,

Can you please share the project and the hex file used to program the device?

I was unable to access the thread that you mentioned. Can you please share the link to the thread again?

Also, can you let me know the steps you followed to get the aws_demo project working? This will help us get some insight as to what might be the issue.

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B
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KoMa_4822621
New Contributor

Hex file attached. The project is too large.

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RodolfoGL
Employee

Kobus,

Could you please print the message from Cypress Programmer when connecting to your board. You should see something like this:

Info : ** Probe-config: kit_CY8CPROTO-062-4343W.cfg

Info : Open On-Chip Debugger 0.10.0+dev-3.0.0.665 (2020-03-20-10:13)

Info : Licensed under GNU GPL v2

Info : For bug reports, read

Info : http://openocd.org/doc/doxygen/bugs.html

Info : debug_level: 2

Info : adapter speed: 1500 kHz

Info : serial: 16190E8B02237400

Info : transport: swd

Info : rst type: soft

Info : efuse: off

Info : sflash restrict: 1

Info : adapter speed: 2000 kHz

Info : ** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable

Info : cortex_m reset_config sysresetreq

Info : cortex_m reset_config sysresetreq

Info : none separate

Warn : SFlash programming allowed for regions: USER, TOC, KEY

Info : tcl server disabled

Info : Listening on port 4445 for telnet connections

Info : CMSIS-DAP: SWD Supported

Info : CMSIS-DAP: FW Version = 1.2.0

Info : CMSIS-DAP: Interface Initialised (SWD)

Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1

Info : CMSIS-DAP: Interface ready

Info : KitProg3: FW version: 2.10.878

Info : KitProg3: Pipelined transfers enabled

Info : VTarget = 3.301 V

Info : kitprog3: acquiring PSoC device...

Info : clock speed 2000 kHz

Info : SWD DPIDR 0x6ba02477

Info : psoc6.cpu.cm0: hardware has 4 breakpoints, 2 watchpoints

Info : psoc6.cpu.cm0: external reset detected

Info : ***************************************

Info : ** Silicon: 0xE402, Family: 0x102, Rev.: 0x11 (A0)

Info : ** Detected Device: CY8C624ABZI-S2D44A0

Info : ** Detected Main Flash size, kb: 2048

Info : ** Flash Boot version: 3.1.0.45

Info : ** Chip Protection: NORMAL

Info : ***************************************

Info : psoc6.cpu.cm4: hardware has 6 breakpoints, 4 watchpoints

Info : psoc6.cpu.cm4: external reset detected

Info : Listening on port 3333 for gdb connections

Info : Listening on port 3334 for gdb connections

Info : accepting 'telnet' connection on tcp/4445

Info : Open On-Chip Debugger

Info : init_target

Info : kitprog3: acquiring PSoC device...

Info : target halted due to debug-request, current mode: Thread

Info : xPSR: 0x41000000 pc: 0x00000190 msp: 0x080ff800

Info : ** Device acquired successfully

Info : ** psoc6.cpu.cm4: Ran after reset and before halt...

Info : target halted due to debug-request, current mode: Thread

Info : xPSR: 0x01000000 pc: 0x0000012a msp: 0x080ff800

Info : flash 'psoc6_2m' found at 0x10000000

Info : flash 'psoc6_2m' found at 0x14000000

Info : flash 'psoc6_2m' found at 0x16000000

Info : flash 'psoc6_2m_efuse' found at 0x90700000

Info : #0 : psoc6_main_cm0 (psoc6_2m) at 0x10000000, size 0x00200000, buswidth 4, chipwidth 4

Info : #1 : psoc6_work_cm0 (psoc6_2m) at 0x14000000, size 0x00008000, buswidth 4, chipwidth 4

Info : #2 : psoc6_super_cm0 (psoc6_2m) at 0x16000000, size 0x00008000, buswidth 4, chipwidth 4

Info : #3 : psoc6_efuse_cm0 (psoc6_2m_efuse) at 0x90700000, size 0x00000400, buswidth 1, chipwidth 1

Info : #4 : psoc6_main_cm4 (virtual) at 0x10000000, size 0x00000000, buswidth 0, chipwidth 0

Info : #5 : psoc6_work_cm4 (virtual) at 0x14000000, size 0x00000000, buswidth 0, chipwidth 0

Info : #6 : psoc6_super_cm4 (virtual) at 0x16000000, size 0x00000000, buswidth 0, chipwidth 0

Info : #7 : psoc6_efuse_cm4 (virtual) at 0x90700000, size 0x00000400, buswidth 1, chipwidth 1

Info : cyp status: OK

Info : cyp_get_mpn

Info : ** Detected device PN: CY8C624ABZI-S2D44A0 SiliconID: E402 Revision: 11 FamilyID: 102 DIE: PSoC6A2M

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KoMa_4822621
New Contributor

Here is the message

Info : [CyBridge] Start API initialization

Info : [CyBridge] Hardware initialization complete (1727 ms)

Info : Connected - KitProg3 CMSIS-DAP HID-0B2114C900020400 FW Version 2.10.878

Info : Selected Device: CY8CPROTO-062-4343W-0B2114C900020400

Info : ** Probe-config: kit_CY8CPROTO-062-4343W.cfg

Info : Open On-Chip Debugger 0.10.0+dev-3.0.0.665 (2020-03-20-17:12)

Info : Licensed under GNU GPL v2

Info : For bug reports, read

Info : http://openocd.org/doc/doxygen/bugs.html

Info : debug_level: 2

Info : adapter speed: 1500 kHz

Info : serial: 0B2114C900020400

Info : transport: swd

Info : rst type: soft

Info : efuse: off

Info : sflash restrict: 0

Info : adapter speed: 2000 kHz

Info : ** Auto-acquire enabled, use "set ENABLE_ACQUIRE 0" to disable

Info : cortex_m reset_config sysresetreq

Info : cortex_m reset_config sysresetreq

Info : none separate

Info : SFlash programming disallowed, see 'sflash_restrictions' command

Info : tcl server disabled

Info : Listening on port 4445 for telnet connections

Info : CMSIS-DAP: SWD Supported

Info : CMSIS-DAP: FW Version = 1.2.0

Info : CMSIS-DAP: Interface Initialised (SWD)

Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1

Info : CMSIS-DAP: Interface ready

Info : KitProg3: FW version: 2.10.878

Info : KitProg3: Pipelined transfers enabled

Info : VTarget = 3.311 V

Info : kitprog3: acquiring PSoC device...

Error: kitprog3: failed to acquire PSoC device

Info : clock speed 2000 kHz

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : Polling target psoc6.cpu.cm0 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : Examination failed, GDB will be halted. Polling again in 100ms

Info : Polling target psoc6.cpu.cm0 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : Examination failed, GDB will be halted. Polling again in 300ms

Info : Listening on port 3333 for gdb connections

Info : Listening on port 3334 for gdb connections

Info : accepting 'telnet' connection on tcp/4445

Info : Open On-Chip Debugger

Info : init_target

Info : ***************************************

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x16000000

Info : mem2array: Read @ 0x16000000, w=4, cnt=1, failed

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x16002004

Info : mem2array: Read @ 0x16002004, w=4, cnt=1, failed

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x402020c4

Info : mem2array: Read @ 0x402020c4, w=4, cnt=1, failed

Info : Error executing event examine-end on target psoc6.cpu.cm0:

Error: /Applications/CyProgrammer_3_0.app/Contents/MacOS/./../CyPGui/openocd/scripts/target/psoc6_common.cfg:278: Error:

Error: in procedure 'init_target'

Error: in procedure 'ocd_process_reset'

Error: in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 270

Error: in procedure 'cy_get_set_device_param' called at file "/Applications/CyProgrammer_3_0.app/Contents/MacOS/./../CyPGui/openocd/scripts/target/psoc6_common.cfg", line 221

Error: in procedure 'show_chip_protection' called at file "/Applications/CyProgrammer_3_0.app/Contents/MacOS/./../CyPGui/openocd/scripts/target/cy_get_set_device_param.cfg", line 189

Error: in procedure 'mrw' called at file "/Applications/CyProgrammer_3_0.app/Contents/MacOS/./../CyPGui/openocd/scripts/target/cy_get_set_device_param.cfg", line 146

Error: at file "/Applications/CyProgrammer_3_0.app/Contents/MacOS/./../CyPGui/openocd/scripts/target/psoc6_common.cfg", line 278

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Info : AP write error, reset will not halt

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: in procedure 'init_target'

Info : SWD DPIDR 0x6ba02477

Info : Polling target psoc6.cpu.cm4 failed, trying to reexamine

Info : SWD DPIDR 0x6ba02477

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xe000ed00

Info : Examination failed, GDB will be halted. Polling again in 100ms

Error: cyp status: ERROR

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KoMa_4822621
New Contributor

I purchased 3 new boards and were able to program successfully. I tried again on the first boards and still get the errors.

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RodolfoGL
Employee

Kobus,

Have you modified your hardware by removing some ZERO ohm resistors and wiring?

I am able to reproduce the problem if you are not powering the PSoC correctly. For instance, If I remove the Jumper from J3, I get the same error message.

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KoMa_4822621
New Contributor

I have tried to power the boards from the second USB connector while programming through the debug connector but that made not difference. 1 of the boards that is no bricked was modified for the Voice on Arm demo and 2 were unmodified so it is not the modification that causes the problem.

Another interesting data point. My Chinese colleagues don’t have the same issue but their silicon is an older revision.

Boards that can be reprogrammed:                                       Boards that are bricked

***************************************               ***************************************

** Silicon: 0xE402, Family: 0x102, Rev.: 0x11 (A0)             ** Silicon: 0xE453, Family: 0x102, Rev.: 0x12 (A1)

** Detected Device: CY8C624ABZI-D44                               ** Detected Device: CY8C624ABZI-S2D44

** Detected Main Flash size, kb: 2048                                  ** Detected Main Flash size, kb: 2048

** Flash Boot version: 3.1.0.45                                              ** Flash Boot version: 3.1.0.378

** Chip Protection: VIRGIN                                                    ** SFlash version: 292144

***************************************               ** Chip Protection: NORMAL

                                                                                                    ***************************************

I purchased brand new boards on Friday and were able to program 2 boards successfully.

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RodolfoGL
Employee

As requested by Rakshith previously, can you provide the steps you performed to setup the project and program the board?

I wonder if you have modified the NAR bits to disable the debug port.

I'm able to program your HEX file multiple times, without bricking the board. I'm also using the same part number:

Info : ** Silicon: 0xE453, Family: 0x102, Rev.: 0x12 (A1)

Info : ** Detected Device: CY8C624ABZI-S2D44

Info : ** Detected Main Flash size, kb: 2048

Info : ** Flash Boot version: 3.1.0.378

Info : ** Chip Protection: NORMAL

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RodolfoGL
Employee

Oh, actually my suspicion was correct. Once I changed the SFlash restrictions to "Erase/Program USER/TOC/KEY allowed", I'm able to reproduce your problem. You are probably disabling the debug port in the NAR bits.

If you have a board that still working, make sure to set the Sflash Restrictions to "Erase/Program Sflash prohibited".

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KoMa_4822621
New Contributor

I have not changed the NAR bits but if you let me know where to look I can check.

Did you program with hex file earlier in the thread? Does that disable the debug port?

Is there any way  to enable the debug port again?

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RodolfoGL
Employee

Yes, after I changed the SFlash restrictions, it seems the debug port is disabled.

We are trying to find a way to make the board workable again. I will keep you posted.

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RodolfoGL
Employee

In the meanwhile, can you please provide the steps to setup and program your project? We want to understand what have you changed in the SFlash user content.

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KoMa_4822621
New Contributor

I received the project from our team in China. I built the project in the IDE and then programmed via the IDE not changing any settings.

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RodolfoGL
Employee

We are consulting our software team to find a way to revert the board. In meanwhile, please use Cypress Programmer with Sflash Restrictions set to "Erase/Program Sflash prohibited".

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KoMa_4822621
New Contributor

I assume these are the default settings. The programmer shows that that "Erase/Program Sflash prohibited" is selected. See attached

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KoMa_4822621
New Contributor

Update. I programmed and reprogrammed the new board that I received from Mouser successfully with the Cypress programmer.

Chip info

Info : ***************************************

Info : ** Silicon: 0xE453, Family: 0x102, Rev.: 0x12 (A1)

Info : ** Detected Device: CY8C624ABZI-S2D44

Info : ** Detected Main Flash size, kb: 2048

Info : ** Flash Boot version: 3.1.0.378

Info : ** SFlash version: 292144

Info : ** Chip Protection: NORMAL

Info : ***************************************

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RodolfoGL
Employee

Hi Kobus,

We confirmed that the amazon-freertos 201910-MTBAFR1951 is setting some internal bits in the SFlash incorrectly, causing the issue you observed.

The newest release, amazon-freertos 202007-MTBAFR41 fixed this issue.

Here is the list of releases:

Tags · cypresssemiconductorco/amazon-freertos · GitHub

We are still working on a method to recover the boards flashed with the old version. If we find a way to do so, we will post here.

View solution in original post

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KoMa_4822621
New Contributor

Thanks Rodolfo for the explanation. Please let me know if there is any way to recover the 3 boards that were bricked.

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RodolfoGL
Employee

Kobus,

Are you able to download a new firmware through OTA? I think what we could do is to download a firmware that enables the SWJ pins, so we can attach to the device over SWD, then erase the SFLASH.

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PeLv_4732496
New Contributor

Hi,

We want to offer a patch to fix this issue. Would you please tell me what exactly results in this problem?

I checked the code and the generated HEX file and do not find the modification of NAR (0x16001a00) in sflash.

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RodolfoGL
Employee

Pengyu, the problem is not related to the NAR (that was my suspicion in the beginning).

The are other parts of the sflash that configures the SWJ pins. More specifically, they are the ones specified in the TRM, Table 14-3. TOC2_FLAGS Bits. Refer to SWJ_PINS_CTL.

If you are able to program a new firmware using OTA, you can enable the SWJ pins in the application, so we can connect to the device again. The code would be something like this:

static void ConfigureSwjP6(void)

{

   /* Note, PSoC6A-BLE-2 and PSoC6A-2M use the same pins and pin configuration */

   /* Pin number */

   const uint32_t POS_TCLK = 7u;

   const uint32_t POS_TMS  = 6u;

   const uint32_t POS_TDI  = 5u;

   const uint32_t POS_TDO  = 4u;

   /* "(Pin Number) - 4" because PORT_SEL1 stores pins 4 to 7 */

   /* Multiplied by 8 because PORT_SEL1 stores each pin's HSIOM in 8 bits */

   const uint32_t HSIOM_POS_TCLK   = 8u * (POS_TCLK - 4u);

   const uint32_t HSIOM_POS_TMS   = 8u * (POS_TMS  - 4u);

   const uint32_t HSIOM_POS_TDI   = 8u * (POS_TDI  - 4u);

   const uint32_t HSIOM_POS_TDO   = 8u * (POS_TDO  - 4u);

   /* Pin number multiplied by a number of bits per drive mode in GPIO_PRTx.CFG register */

   const uint32_t CFG_POS_TCLK = 4u * POS_TCLK;

   const uint32_t CFG_POS_TMS  = 4u * POS_TMS;

   const uint32_t CFG_POS_TDI  = 4u * POS_TDI;

   const uint32_t CFG_POS_TDO  = 4u * POS_TDO;

#if CY_FB_OPT_PSVP == 0

   const uint32_t DM_TCLK = 0xBu; /* input enabled=1, drive mode=3 */

   const uint32_t DM_TMS  = 0xAu; /* input enabled=1, drive mode=2 */

   const uint32_t DM_TDI  = 0xAu; /* input enabled=1, drive mode=2 */

#else

   /* Note, PSVP requires drive mode=5 for all SWJ input pins */

   const uint32_t DM_TCLK = 0xEu; /* input enabled=1, drive mode=5 */

   const uint32_t DM_TMS  = 0xEu; /* input enabled=1, drive mode=5 */

   const uint32_t DM_TDI  = 0xEu; /* input enabled=1, drive mode=5 */

#endif /* CY_FB_OPT_PSVP == 0 */

   const uint32_t DM_TDO   = 0x6u; /* input enabled=0, drive mode=6 */

   HSIOM->PRT[6u].PORT_SEL1 = ( (uint32_t)P6_7_CPUSS_SWJ_SWCLK_TCLK << HSIOM_POS_TCLK)

   | ( (uint32_t)P6_6_CPUSS_SWJ_SWDIO_TMS  << HSIOM_POS_TMS )

   | ( (uint32_t)P6_5_CPUSS_SWJ_SWDOE_TDI  << HSIOM_POS_TDI )

   | ( (uint32_t)P6_4_CPUSS_SWJ_SWO_TDO   << HSIOM_POS_TDO );

   GPIO_PRT6->CFG = (DM_TCLK << CFG_POS_TCLK) | (DM_TMS << CFG_POS_TMS)

   | (DM_TDI  << CFG_POS_TDI ) | (DM_TDO << CFG_POS_TDO);

}

#endif /* CY_FB_OPT_TVII == 0 */

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PeLv_4732496
New Contributor

Hi,

Thank you for the explanation.

Our patch is to avoid people who use our demo from bricking their board. If my understanding is correct, the solution is to explicitly set the cyToc[126] = 0x00000040 and change cyToc[127] to the correct crc value as well in cybsp_serial_flash_prog.c.

I believe these changes would fix the issue and avoid the demo from bricking boards.

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RodolfoGL
Employee

Hi Pengyu,

I would suggest to upgrade to the amazon-freertos-20207. If you still want to use the amazon-freertos-201908, then you can set TOC2_FLAGS=0x000000C2 in cybsp_serial_flash_prog.c. This would:

- Increase the CM0+ CPU clock frequency from 8MHz to 50 MHz while running the boot code.

- Enable SWJ_PINS_CTL

- Disable app authentication (I guess you are not using this?)

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PeLv_4732496
New Contributor

It's helpful for us. Thank you for your explanation and suggestions.

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Rakshith
Moderator
Moderator

Hello Kobus,

You will be contacted by a Cypress, an Infineon Technologies Company, representative regarding the replacement of your kit.

Thanks and Regards,

Rakshith M B

Thanks and Regards,
Rakshith M B
ChMa_3807401
New Contributor II

Hi Rakshith,

My kit has exactly the same issue. If there's no fix to come, can you have your representative contacting me as well?

Thanks,

Charles

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Rakshith
Moderator
Moderator

Hi Charles, 

We will get in touch with you shortly.

Thanks and Regards,
Rakshith M B
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