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PSoC 6 MCU

CoreyW_81
Employee

Hello Community -

Has anyone seen the P6 module still receiving power even with R28 (a 0 Ohm Jumper) removed and J3 not jumpered?  I measure around 2.5V on P6_VDD on J3?  Looking at the schematic, it seems like either of the 2 LED's (LED3 and LED4) might be backpowering the P6 module.  Same for I2C_SCL and I2C_SDA, as well as UART_RX and UART_TX.

While this is possibly going to mess up my current measurement across J3, will this also allow some designs to actually operate in the module by powering through the pins.

And, is this going to be detrimental to the module?

In PSoC Creator, with R28 off and J3 unjumpered, I can acquire the part for programming (at least the the M0+ core) but when I try to program, it fails.  The fact that I can even acquire the part via the sneak paths is a concern.

Please let me know if this is a known concern with the board and where this strange behavior is documented.

Thanks

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1 Solution
SanjeevG_16
Employee

Yes. As you said, there is back-power provided due to say LED's, I2C pull-up lines. Here, the voltage domains in the PSoC6 chip are powered if the voltage in the PSoC6 pin is greater than that of the domain. As you removed R28, the Vtarg powers the chip through either LED or the I2C with the resistors in these lines providing a drop in voltage at P6_VDD.

The idea here is that the LED current consumption or current provided due to I2C pull-up should not come into picture during current measurement.

The current consumed only by the  PSoC 6 chip will be shown by the header J3.

PSoC 6 programs even if the VDDIO lines in the SWD port and the VDDD voltage are as low as 1.8V.

I don't think it is a concern or that it has detrimental effect to the module. If there is enough current to power the internal circuitry, the programming will take place or else it won't.

View solution in original post

1 Reply
SanjeevG_16
Employee

Yes. As you said, there is back-power provided due to say LED's, I2C pull-up lines. Here, the voltage domains in the PSoC6 chip are powered if the voltage in the PSoC6 pin is greater than that of the domain. As you removed R28, the Vtarg powers the chip through either LED or the I2C with the resistors in these lines providing a drop in voltage at P6_VDD.

The idea here is that the LED current consumption or current provided due to I2C pull-up should not come into picture during current measurement.

The current consumed only by the  PSoC 6 chip will be shown by the header J3.

PSoC 6 programs even if the VDDIO lines in the SWD port and the VDDD voltage are as low as 1.8V.

I don't think it is a concern or that it has detrimental effect to the module. If there is enough current to power the internal circuitry, the programming will take place or else it won't.

View solution in original post

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