ADC Reading Affected by VDDA Value

[PaGy_1246781]

Hello All,

I have a project using PSoC63 in which the Vdd (and Vdda) varies from 2.1 to 2.5 V.  I am using the Scanning SAR ADC as follows:

• Differential input across a low impedance (shunt resistor).
• VRef is System Bandgap (1.2V).
• Input common mode voltage is near Vss.

It appears that, with a constant input voltage, as Vdd (Vdda) increases, ADC readings increase somewhat.  I don't have actual numbers - this is simply a consistent pattern that I have observed.

Has anyone else seen this behavior?  If so, do you have a fix?

Paul

[ARH]

I was hoping someone was gonna answer this question... because Im not sure.

My first thought was that the reference is 1% ... so as long as your "somewhat" was less than 1% then OK.

The reason I was hoping someone would answer is that Im not an analog guy.... however, I know that the SAR sequencer has a sample and hold circuit... so there might be something to do with the input impedance of that circuit and the output impedance of your circuit.

I suspect that you were onto the right reason with the input voltage being near 0... but im not at all sure... which again is the reason I was hoping to see a real answer.

[MotooTanaka]

Hi,

I wonder which tool you are using...

If you are using PSoC Creator, ADC's reference is set in the ADC Config's Vref select

And I think you are selecting VDDA or VDDA/2, whose value changes when VDDA voltage changes.

If you select system bandgap, the reference voltage should be stable

when VDD/VDDA changes.

But you must make sure that ADC's input voltage is in the range of 0~1.2V.

If you are using ModusToolbox,

in the main.c of  ADC_basic example ADC configure is done as below

/* Default ADC configuration */
const cyhal_adc_config_t adc_config = {
        .continuous_scanning=false, // Continuous Scanning is disabled
        .average_count=1,           // Average count disabled
        .vref=CYHAL_ADC_REF_VDDA,   // VREF for Single ended channel set to VDDA
        .vneg=CYHAL_ADC_VNEG_VSSA,  // VNEG for Single ended channel set to VSSA
        .resolution = 12u,          // 12-bit resolution
        .ext_vref = NC,             // No connection
        .bypass_pin = NC };       // No connection

Here, vref is also set to VDDA, if you want to use System Bandgap,

change CYHAL_ADC_REF_VDDA to CYHAL_ADC_REF_INTERNAL.

This value is defined in cyhal_adc.h

/** Possible selections for ADC reference */
typedef enum
{
    CYHAL_ADC_REF_INTERNAL,     //!< Internal reference. See the BSP documentation for the value of this reference. (Default)
    CYHAL_ADC_REF_EXTERNAL,     //!< Reference from external pin.
    CYHAL_ADC_REF_VDDA,         //!< Reference from VDDA (analog supply)
    CYHAL_ADC_REF_VDDA_DIV_2,   //!< Reference from VDDA (analog supply) divided by 2
} cyhal_adc_vref_t;

 

moto

[Vasanth]

Hi Paul,

Will you be able to share the code on how you have configured the ADC. The bandgap reference is not expected to vary with VDDA. One more additional question I have is that , what is the source of the shunt resistor ? Is it somehow related to VDDA ?

Best Regards,
Vasanth

[PaGy_1246781]

Hi Vasanth and all,

In PSoC Creator, I have set Aref to Local 1.2V.  But since I am using a PSoC63 in which the M0+ core is locked down, it is possible that the M0+ code set it differently, but I doubt it.  The supplier says that my Design Wide Resources settings would override theirs.

I don't think Aref is set to VDDA or VDDA/2 because, if it were so, I would expect my readings to decrease as VDDA increases (signal becomes smaller with respect to VDDA).  Instead, readings increase in value as VDDA rises.

I should point out that I am using two different ADC configurations.  Configuration 0 is a differential measurement across a 6 Ohm resistor.  The negative input is near Vss at measurement time.  Configuration 1 is a single-ended input to measure VDDA.  In this configuration, I can measure up to 2.4V.

Periodically, the ADC is set to config 1 and VDDA measurement is done.  After that, the ADC is switched to config 0 and the differential measurement is made.  Many samples are summed over a 50 ms interval.

Is it possible that there is some "carry over" from config 1 into config 2?  Is there some minimum wait time before using a new ADC configuration?  Any suggestions would be appreciated.

Paul