AD config

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JCD
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Sorry to disturb everyone.

I encountered a very difficult problem.

The chip I use is CY8C614ABZI-S2F04.

I configured the AD pin and used AMUXA and AMUXB. The code is as follows:

Cy_GPIO_Pin_FastInit(GPIO_PRT9, 3,CY_GPIO_DM_ANALOG, 1, P9_3_AMUXA);
Cy_SAR_SetAnalogSwitch(SAR, CY_SAR_MUX_SWITCH0,
(uint32_t)(SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk), CY_SAR_SWITCH_CLOSE);
Cy_SAR_SetSwitchSarSeqCtrl(SAR, (uint32_t)(SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk), CY_SAR_SWITCH_SEQ_CTRL_ENABLE);
SAR->CHAN_CONFIG[IO_AD_CH8] = (uint32_t)(config_IO_AD_CH8);

But the problem appeared, always generating DSI interrupt, causing the program to enter CY_HALT(). I don't know where the problem is.

Please help, thank you very much.

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1 Solution
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

Will you able to share more information about the project and its settings ? Additionally are you using the latest version of the MTB? It has supported for non-dedicated pins as SAR ADC input through the AMUXBUS using configurator. If you still want to use PDL, refer this KBA too : https://community.cypress.com/t5/Knowledge-Base-Articles/Route-Non-Dedicated-Pins-as-SAR-ADC-Inputs-...

 

Best Regards,
Vasanth

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3 Replies
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

Will you able to share more information about the project and its settings ? Additionally are you using the latest version of the MTB? It has supported for non-dedicated pins as SAR ADC input through the AMUXBUS using configurator. If you still want to use PDL, refer this KBA too : https://community.cypress.com/t5/Knowledge-Base-Articles/Route-Non-Dedicated-Pins-as-SAR-ADC-Inputs-...

 

Best Regards,
Vasanth

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JCD
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Thank you very much for your answers.

My current situation is that the AD value can be retrieved, but a DSI interrupt will be generated after a period of time, and then enter CY_HALT(), and the program will stop running. I compared my AD configuration code with yours, and it seems that the only difference lies in this:

HSIOM->AMUX_SPLIT_CTL[1] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;

  HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;

You made this configuration, but I didn’t。

This is my current understanding.

I don't know if you have any ideas.

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Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

AMUX split control registers are need to be controlled when the non dedicated pin from a difference amuxbus section is used. As in your case port 9 is used, this is not required. You can see analog routing for more clarity on what I have said. Now are you sure about the origin of the interrupt? What are all the other resources in your project? Do you see this interrupt if the ADC part of the code is disabled ? Additionally will you be able to tell the steps to recreate the issue?

Best Regards,
Vasanth

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