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PSoC 5, 3 & 1 MCU

Ramanf
New Contributor

Hi,

i am trying to connect one SAR ADC to a two channel filter. i expect to filter each sample on both filters simultaneously.

i tried to follow ADC to Filter –Dual Channel 16-Bit Streamingusing DMA–PSoC® 3 / PSoC 5  EP58353

but i don't see any ADC nrq. first i attempted to implement ADC to SRAM and that word fine.

please help me to configure every thing.

Thanks

 

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1 Solution
odissey1
Honored Contributor II

Ramanf,

1. To transfer with DMA the 12-bit data from ADC_SAR to 16-bit Filter input, the Filter needs proper coherency setting for each channel

See: Filter Channel B 16 bit DMA issue 

// For 9-16 bits filter resolution, Filter coherency should be MID, Dalign should be enabled
Filter_PLC_SetCoherency(Filter_PLC_CHANNEL_A, Filter_PLC_KEY_MID );
Filter_PLC_SetCoherency(Filter_PLC_CHANNEL_B, Filter_PLC_KEY_MID );

Filter_PLC_SetDalign(Filter_PLC_STAGEA_DALIGN | Filter_PLC_HOLDA_DALIGN, Filter_PLC_ENABLED);
Filter_PLC_SetDalign(Filter_PLC_STAGEB_DALIGN | Filter_PLC_HOLDB_DALIGN, Filter_PLC_ENABLED);

 

Note that using simple DMA transfer from ADC_SAR to Filter results in signal amplitude loss due to two factors. The ADC output is 12-bit unsigned, while staging register expecting 16-bit signed value for full-scale output, so the signal amplitude will loose 4-bits. This will lead to lower output amplitude and lower resolution. Such loss of output amplitude can be partially compensated by increasing Filter Gain, which can be increased up to 2. The gain loss can be compensated in software (on the USB host side), but the loss of resolution is not.

The two examples in the link above show a way to compensate for the sign and amplitude loss using PSoC5 hardware. 

 

2. In your code both Filter channels are configured for Bandpass mode, so the output of the Filter is signed (both positive and negative values are present). I would use int16 for output RAM buffers instead of uint16 (though it may be OK, if the data are converted back to signed somewhere at the USB host).

int16 ADC_sample[NO_OF_SAMPLES]={0};
int16 ADC_sample_2[NO_OF_SAMPLES]={0};  

 

3. To fire interrupt isr_PLC_FLT, the flag DMA_FLT1__TD_TERMOUT_EN must be enabled:

/* DMA Configuration for DMA_FLT1 */

CyDmaTdSetConfiguration(DMA_FLT1_TD[0], (2*NO_OF_SAMPLES), DMA_FLT1_TD[0], CY_DMA_TD_INC_DST_ADR | DMA_FLT1__TD_TERMOUT_EN );

 

4. The Sample & Hold in front of the ADC_SAR, which are both triggered simultaneously, seems unnecessary ("Don't buffer buffered buffer!").

 

5. The A and B channels of the filter are configured for approx. 60-90kHz and 100-120kHz respectfully. The Filter taps (128) can be distributed proportionally to center frequency to optimize filter performance (currently is 52/53 - causing output signal 1/2 sampling step shift between the channels).

/odissey1

PLC01_1adcDma_A.png

View solution in original post

4 Replies
odissey1
Honored Contributor II

Ramanf,

Please take look on this project (ADC_SAR-Filter-Vdac)

ADC_SAR - Filter - VDAC streaming demo using DMA  

It covers some issues of streaming data from ADC_SAR to the Filter and to VDAC8. You can use it as a stub for adding the Channel_B Filter.

Note that ADC_SAR doesn't show the sign bit correctly, like DelSig-ADC (at least for me).

 

What is ADC input signal: 0-2V, 1+/-1V?

What is frequency range?

What filters do you want to implement, LP, HP, BP?

/odissey1

 

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odissey1
Honored Contributor II

Ramanf,

1. To transfer with DMA the 12-bit data from ADC_SAR to 16-bit Filter input, the Filter needs proper coherency setting for each channel

See: Filter Channel B 16 bit DMA issue 

// For 9-16 bits filter resolution, Filter coherency should be MID, Dalign should be enabled
Filter_PLC_SetCoherency(Filter_PLC_CHANNEL_A, Filter_PLC_KEY_MID );
Filter_PLC_SetCoherency(Filter_PLC_CHANNEL_B, Filter_PLC_KEY_MID );

Filter_PLC_SetDalign(Filter_PLC_STAGEA_DALIGN | Filter_PLC_HOLDA_DALIGN, Filter_PLC_ENABLED);
Filter_PLC_SetDalign(Filter_PLC_STAGEB_DALIGN | Filter_PLC_HOLDB_DALIGN, Filter_PLC_ENABLED);

 

Note that using simple DMA transfer from ADC_SAR to Filter results in signal amplitude loss due to two factors. The ADC output is 12-bit unsigned, while staging register expecting 16-bit signed value for full-scale output, so the signal amplitude will loose 4-bits. This will lead to lower output amplitude and lower resolution. Such loss of output amplitude can be partially compensated by increasing Filter Gain, which can be increased up to 2. The gain loss can be compensated in software (on the USB host side), but the loss of resolution is not.

The two examples in the link above show a way to compensate for the sign and amplitude loss using PSoC5 hardware. 

 

2. In your code both Filter channels are configured for Bandpass mode, so the output of the Filter is signed (both positive and negative values are present). I would use int16 for output RAM buffers instead of uint16 (though it may be OK, if the data are converted back to signed somewhere at the USB host).

int16 ADC_sample[NO_OF_SAMPLES]={0};
int16 ADC_sample_2[NO_OF_SAMPLES]={0};  

 

3. To fire interrupt isr_PLC_FLT, the flag DMA_FLT1__TD_TERMOUT_EN must be enabled:

/* DMA Configuration for DMA_FLT1 */

CyDmaTdSetConfiguration(DMA_FLT1_TD[0], (2*NO_OF_SAMPLES), DMA_FLT1_TD[0], CY_DMA_TD_INC_DST_ADR | DMA_FLT1__TD_TERMOUT_EN );

 

4. The Sample & Hold in front of the ADC_SAR, which are both triggered simultaneously, seems unnecessary ("Don't buffer buffered buffer!").

 

5. The A and B channels of the filter are configured for approx. 60-90kHz and 100-120kHz respectfully. The Filter taps (128) can be distributed proportionally to center frequency to optimize filter performance (currently is 52/53 - causing output signal 1/2 sampling step shift between the channels).

/odissey1

PLC01_1adcDma_A.png

View solution in original post

Ramanf
New Contributor

Thank you.

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odissey1
Honored Contributor II

ramanf,

I believe that ADC to dual Filter (A/B) project demo has never been posted on this forum. If permitted consider sharing a demo project with community. 

/odissey1

 

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