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PSoC 5, 3 & 1 MCU

New Contributor

Hello,

i am new to the world of PSOC and have more of a digital, than analog background, so i hope my question is somewhat valid.

I'm doing a project and try to build a signal simulator for it - very weak signals. I use the CY8CKIT-059 kit. For basic testing i use this setup:

DAC_ADC.png

The WaveDAC is an iSource. The VDAC is there to pull the signal to zero, so i can lower the input range of the ADC. The digital filter in the end is there so i can calculate the signal to noise ratio (SNR). In this setup i get a sinus signal between about 0 - 2.2V.

My goal is to dampen the signal. just in this setup i have two possibilities to do so

a) lower the WaveDAC output range to either 0-255 uA (8x smaller) or 0-32uA (64x smaller)

b) make the resistor smaller

a) works perfectly. the ADC reads signals that are about as much smaller as they should be. if I test with an oscilloscope at the Testpoint (TP) it's somewhat the same.

b) on the other hand does not at all, what it should (or at least i think it should).
if i replace the 1K Resistor at R_DAC with a 10 Ohm resistor, the signal should be 100x smaller (0-20mV). if i test with the oscilloscope at the TP it is roughly in the correct neighborhood. the signal has a 20mV offset and is only 66x smaller, but that is still much closer, than what the ADC reads. Peak-to-Peak the ADC gets 220mV, so only 10x smaller instead of 100x.

if I use a 1 Ohm resistor, it should be 1000x smaller (0-2mV). The oscilloscope tells me of 8mV peak-to-peak (275x smaller), but the ADC reads 175mV peak-to-peak (only 12x smaller!!)

What do i do wrong? The ADC is set to continous and bypass buffer, so there should be no gain, or?

The signals look fine - i get an SNR of mostly over 50db.

I plan on trying out current dividers and opamps to dampen the signal, but would rather like to keep it as simple as possible.

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Honored Contributor II

misc,

You forgot that all wire connections inside PSoC have hundreds of oHm resistance (typ. 200-600 oHm), which should be included in your calculations. Try to modify your schematic using 2 pins: one for IDAC8 output, with external resistor, and another pin for ADC input. This way  the effect of internal resistances should be cancelled.

For measurement of very weak signals they must be amplified first using Opamp (e.g x100). And the ADC resolution shoud be set to 20 bits. The simplest way is to use external 24-bit ADC with built-in Opamp, like HX711, which is available for under $1.

HX711: 24-bit Delta Sigma ADC interface for weight scale using PSoC

It gives at least an order of magnitude higher sensitivity, than could be obtained using PSoC hardware alone.

/odissey1

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Honored Contributor II

misc,

You forgot that all wire connections inside PSoC have hundreds of oHm resistance (typ. 200-600 oHm), which should be included in your calculations. Try to modify your schematic using 2 pins: one for IDAC8 output, with external resistor, and another pin for ADC input. This way  the effect of internal resistances should be cancelled.

For measurement of very weak signals they must be amplified first using Opamp (e.g x100). And the ADC resolution shoud be set to 20 bits. The simplest way is to use external 24-bit ADC with built-in Opamp, like HX711, which is available for under $1.

HX711: 24-bit Delta Sigma ADC interface for weight scale using PSoC

It gives at least an order of magnitude higher sensitivity, than could be obtained using PSoC hardware alone.

/odissey1

View solution in original post

New Contributor

Bota,

thank you so much for setting me on the right path. I've implemented your suggestion with external routing like this:

Ext1.png

and voilá...i get now a 28.4x dampening instead of 10x. Also the noise is slightly rising from 880uV to 1080uV, but that is to be expected with external cabels.

So I took your advice a bit further and mad the reference VDAC also connecting externally to the ADC:

Ext2.png

That made it somewhat worse from the last setup  - "only" 20.8x dampening, but lower noise - only 760uV. Now my interest was peeked and i tried to make an iDAC out of the VDAC, because those have these direct low resistance output pins i also use for the WaveDAC. So i changed the setup to this:

Ext3.png

The result was very good...the ADC measured now a dampening of 36x, so best setup yet. Also the noise went down even further to only 630uV. But since the signal is now dampened considerably, i get an SNR of under 50db. To clear up the signal for the ADC even further i added some decoupling capacitors like this:

Ext4.png

This not only cleared up the signal, but brought it also closer to the theoretical dampening factor. with this setup i get an astounding 48x (46.5mV peak-to-peak) dampening with only 152uV peak-to-peak noise. It comes to an SNR of 57.8db. nice.

Nonetheless my PSOC enthusiasm has been a little bit dampened by realizing this solution. Having to do many things externally, especially the routing defeats the purpose of the PSOC to a certain degree i believe.

thank you for your help bota once more. I'm happy with the result and can go in deeper from here.

your suggestion with the HX711 is much apreciated and all the work you have done with your example. unfortunately the 20bit setting doesn't help me since the signal i try to emulate looks like 1.5 sinus waves and is at around 15hz. the 20 bit setting with its max 60SPS and the 10SPS of the HX711 can't resolve those signals sufficiently. with 18bits i get nearly 1ksps, so 65 samples per sinus period.

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Honored Contributor II

MiSc,

The DelSig-ADC S/N depends on the Vref and clock stability. To improve S/N I recommend to use internal Vref, with bypass capacitor (which is already attached onboard the KIT-059, Pin_3[2] or Pin_0[3]):

KIT-059: annotation component for CY8CKIT-059 PSoC5LP Prototyping Kit

The S/N improves further if DelSig-ADC clock is stabilized by external XTAL (e.g. 24MHz), please check the datasheet re effect of the clock stability.

It is not clear the purpose of the IDAC on the ADC ref channel. I would use ADC in the single referenced mode (which needs a single input pin), or in differential mode, with ref channel attached to the 10oHm resistor Gnd (to cancel ground loop noise).

The ADC input must be buffered, which allows for some extra gain settings. For example gain 8x gives  ADC full scale +/- 0.125V.

Can you describe what is the goal of the project? To measure sine amplitude? If so, how do you convert digitized sine into the amplitude value?

/odissey1

New Contributor

Bota,

thanks for all your help.

To clarify. The projects signals sine amplitude is not much a of concern atm. the 1.5 sine wave signal occurance is faint and should be just be detected and counted. There is an existing older ADC prototype with all electronics and some algorithms following the digitalization for the detection of the signal within the data stream. What i'm doing at the moment is trying to build a signal simulator, where i can create these signals in a controlled fashion in order to test the existing detector and measure improvements when changing it. Using the simulator, i know how many signals i created and compare it to the amount detected (false positives / false negatives). Also, if i have a relatively clean signal i can add to the signal random noise in a specific magnitude and deternine how noisy the environment can be before detection suffers.

This is one of the reasons why i'm looking at the SNR.

At the moment I use the PSOC ADC just to control how well the signal is formed and how much noise there is. I start out with a bit stronger signals (>1mV) to compare the different dampening possibilities, so i don't need any active gain in the ADC at the beginning. But later i will add gain for sure. If at the end the ADC of the PSOC comes anywhere close to the existing system, all the better - then we'll switch to the PSOC also for the detection. This would be a bonus, but is not my focus at the moment.

To your suggestions..i had a small conversion error in my code, so the absolute values like the dampening factors i posted in the last post are a bit lower in reality, but in principle it all stayed the same.

The S/N improves further if DelSig-ADC clock is stabilized by external XTAL

I'll have a look at that at some point further down the line. I'm sure it'll help, thanks. I'll report.

To improve S/N I recommend to use internal Vref, with bypass capacitor (which is already attached onboard the KIT-059, Pin_3[2] or Pin_0[3])

that improved the situation considerably! thank you. i didn't know the KIT-059 already had the capacitors attached. In the 10Ohm example

Ext4.png

it ended up dampening insted of 35x now 58x, so much closer to the theoretical dampening factor of 100x. especially the noise improved from 500uV peak-to-peak to 150uV! the SNR just lowered by 4db compared to the full signal.

It is not clear the purpose of the IDAC on the ADC ref channel. I would use ADC in the single referenced mode (which needs a single input pin), or in differential mode, with ref channel attached to the 10oHm resistor Gnd (to cancel ground loop noise).

the iDac is only used, when the signal is >130mV. in this case i can eliminate the DC offset by setting the iDAC to the DC offset value. now i can set the ADC to the lowest fitting input range. For example a 0-500mV sine can be dragged to -250 - +250 and the ADC can be set to this lower input range.the results i get are more comparable this way. but you are right with smaller signals i used your ground suggestion and the results are the same

Ext5.png

If i use a VDAC on the other hand instead of an iDAC the results are much worse (10x less dampening and 11db lower SNR), because the VDAC doesn't have a short route to a pin like the the iDACs have, so higer resistance and more noise.

The smallest signals i produced with only the two dampening methods is with 32uA and 10Ohm 1230x - 1.8mV large signals and 90uV noise at an SNR of almost 30db.

The ADC input must be buffered, which allows for some extra gain settings. For example gain 8x gives  ADC full scale +/- 0.125V.

if i buffer it and get the gain, sps drops significantly - an 8x gain lowers it to 187sps from 1ksps...only 12samples per period might be sufficient, but when i start putting gain on the signal later, better use an opamp for that beforehand and keep the samplerate as it is, no?

so once again. i really appreciated your help....

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