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PSoC 5, 3 & 1 MCU

New Contributor II

I would like to make an 8k block at top of flash for eeprom. I see where bootloadable can be set to allow this. What's confusing is the examples only show setting up small arrays and filling them without any regard to memory address, etc. I want to set up something more organized like the smaller eeprom component where you can define fixed addresses. I guess I want to tell the linker where I want my em_eeprom arrays to reside or maybe just create one big 8k array and then index into it as needed. Any suggestions?

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New Contributor II

I found that something like this works for reading and writing using the em_eeprom flash write functions.

   


#define USRFLSH_BASE 262144 - USRFLSH_SIZE
#define ptr_userFlsh ((uint8 const *) USRFLSH_BASE)

   

The flash write function works fine with pointers to sram source and flash destination. It only gets messy if your application is a bootloadable like mine. You have to tell the bootloadable component the size of your user flash area. It must be at the top of flash. Also, very important, you can't write to the top row of flash or your application will crash on the next power on. The bootloader uses the top 64 bytes.

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New Contributor II

I found that something like this works for reading and writing using the em_eeprom flash write functions.

   


#define USRFLSH_BASE 262144 - USRFLSH_SIZE
#define ptr_userFlsh ((uint8 const *) USRFLSH_BASE)

   

The flash write function works fine with pointers to sram source and flash destination. It only gets messy if your application is a bootloadable like mine. You have to tell the bootloadable component the size of your user flash area. It must be at the top of flash. Also, very important, you can't write to the top row of flash or your application will crash on the next power on. The bootloader uses the top 64 bytes.

View solution in original post

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