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Easiest and most precise would be to run BusClock at 48MHz and define a clock of 16MHz which then will use internally a divider of 3. Alternatively you can set the PLL frequency to 48MHz, keep the BusClock at 24MHz and defining a clock with 16MHz derived (unsynchronized) from PLL. Lastly you are free to use a 48MHz clock as input to a Timer and divide it by three.
The trick is that you need an internal clock running at a multiple of your desired 16MHz (a reference of 32MHz instead of 48MHz would have worked as well).
I hope you can see now that the clock definition and distribution in a PSoC is more flexible than you have seen so far.