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PSoC™ 5, 3 & 1 Forum Discussions

greg79
PSoC™ 5, 3 & 1
I wonder how one would implement an envelope generator for a synthesizer with UDB or LUT? An envelope generator is a finite state machine so it makes ... Show More
luisji
PSoC™ 5, 3 & 1
A complaint
solved msg Solved
How can I get profesional support direct from Cypress, instead of this thing based on contributors??  Because I have 2 months dealing with this system... Show More
luisji
PSoC™ 5, 3 & 1
In electro-tech-online I asked about my need of making a device wich could generate a sinusoidal signal (by PWM method) with a 18F4550 Ucontroller, bu... Show More
Mihai
PSoC™ 5, 3 & 1
Hello all, I am trying to stop a DMA transfer at a specific moment using the trq pin. As nowhere in the documentation a timing diagram is shown with t... Show More
Y_r
PSoC™ 5, 3 & 1
Hello Community and @MotooTanaka san,I am trying to get a MicroSD card adapter with an SPI interface to interface and work with the PSOC 5LP. I have b... Show More
Len_CONSULTRON
PSoC™ 5, 3 & 1
Hi, I'm doing some advanced DMA operations.  One of the advance techniques needs the TRQ input to the DMA component. I'm having difficulty GUARANTEEin... Show More
greg79
PSoC™ 5, 3 & 1
At the risk of sounding ignorant, can one create a composite audio, MIDI and serial USB interface with PSOC 5? 12 Mbps seems plenty but I wonder if th... Show More
AnSa_1225656
PSoC™ 5, 3 & 1

How to detect a baud rate change on PC change on a on a USBFS CDC device?  Driver issue?  Bug?

USBFS config attached

Anonymous
PSoC™ 5, 3 & 1
Using a full duplex UART in a PSoC5 design.I don't understand how the interrupts work when the RX Buffer Size is > 4.From the data sheet:When the (Rx/... Show More
jlsilicon
PSoC™ 5, 3 & 1
PSoc5LP - is ADC_SAR Pin - still reserved if AMux is used ? If I am using ADC_SAR - I need to reserve either P0.2 or P0.4 on the 'Pins' page,  but I c... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.