PSoC™ 5, 3 & 1 Forum Discussions
I wonder how one would implement an envelope generator for a synthesizer with UDB or LUT? An envelope generator is a finite state machine so it makes sense implementing one with UDB.
What I'm interested is if it even makes sense to implement hardware envelope instead of software one? I'm concerned multiple envelope generators would take up too much memory, CPU time or hog DMA channels. Thank you for the help in advance!
Show LessHow can I get profesional support direct from Cypress, instead of this thing based on contributors?? Because I have 2 months dealing with this system and I have not been helped in the way I need. Is there somebody who really care in this company???
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In electro-tech-online I asked about my need of making a device wich could generate a sinusoidal signal (by PWM method) with a 18F4550 Ucontroller, but it seem it is not possible. Someone named Dana suggested me to see the information about this cypress device. So, the questions are:
1. Is it possible to make a threephasic 5 KHz signal (3 120 degrees unphased signals), wich could be used by a power stage to handle about 1 ampere each branch in some kind of power transistors?
2. If the signal is analog, is it a way to isolate the control stage from the power stage?
3. Is it possible to stop or restart this signals with a Ucontroller signal? Or further, to control amplitude?
4. Do this device is sold and there are existences now on Mouser, Arrow or DigiKey?
Thank you for your time
Luis
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Hello all,
I am trying to stop a DMA transfer at a specific moment using the trq pin.
As nowhere in the documentation a timing diagram is shown with the trq input, i've used a clock on the trq signal until the nrq is generated.
But this creates some problems:
- when i use the trq as mentioned above i have 2 extra transfers than i should ( i am using an analyzer on the drq line)
- without the trq i do not have this behaviour
Is there any changes that the trq might force more transfers?
Show LessHello Community and @MotooTanaka san,
I am trying to get a MicroSD card adapter with an SPI interface to interface and work with the PSOC 5LP.
I have been trying to read through the SPI datasheet but there's no mention of using an SD card.😬
Can anyone please share any example project of successful interfacing of an SPI-based SD card adapter with PSOC 5LP?
Or the steps on how to and where to start with? Pin connections? PSOC Creator components to use?...
I have a little understanding of the working of the FAT filesystem.
Regards,
Yash
Hi,
I'm doing some advanced DMA operations. One of the advance techniques needs the TRQ input to the DMA component.
I'm having difficulty GUARANTEEing that the rising edge of the TRQ terminates the current DMA operation.
As an example of the issue, I've modified the program used in the Cypress-supplied App note "001-84810_AN84810_-_PSoC_3_and_PSoC_5LP_Advanced_DMA_Topics".
It replaces the ADC with a WaveDAC8 generating a sine wave and is clocked by an external clock of 100KHz. The DMA moves the wave data in the WaveDAC8 to the VDAC8 data register. This regenerates the sinewave to the pin assigned to the output of the VDAC8.
When you press on the switch (P2.2) on the CY8CKIT-059, the rising edge usually is ignored. after usually many presses, the TRQ is respected and the indefinite DMA transfer is terminated.
I suspect I either didn't set up the SW configuration correctly or the HW state logic is not correct (or both).
I would appreciate understanding what I am missing.
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At the risk of sounding ignorant, can one create a composite audio, MIDI and serial USB interface with PSOC 5? 12 Mbps seems plenty but I wonder if there are any limitations. Thank you for your kind answers in advance.
Show LessHow to detect a baud rate change on PC change on a on a USBFS CDC device? Driver issue? Bug?
USBFS config attached
Using a full duplex UART in a PSoC5 design.
I don't understand how the interrupts work when the RX Buffer Size is > 4.
From the data sheet:
When the (Rx/Tx) Buffer size is set to a value greater than 4, the UART component uses the internal interrupts to move the data from Hardware FIFO to a software FIFO. In this case, use the internal ISR to add custom code to process the data in the "User Code" regions.
Note External interrupts are generated only with respect to the Hardware FIFO.
Does the ISR_UART_RX (auto-generated) fire when the received data overflows the RX Buffer Size that I have specified? Or does it fire after each byte is received?
I have looked at the example projects and it's not clear.
Does the internal interrupt work in the background to transfer the bytes into the buffer, or does it trigger the ISR_UART_RX auto-generated code?
In my application, the RX will received data from another internal board, so I know exactly how many bytes to expect (46 bytes). So if I can fire the ISR when that many bytes are received that's fine.
Thanks
dan
Show LessPSoc5LP - is ADC_SAR Pin - still reserved if AMux is used ?
If I am using ADC_SAR - I need to reserve either P0.2 or P0.4 on the 'Pins' page, but I connected the AMux(4) up to the ADC_SAR on the 'TopDesign' page.
Is the ADC_SAR P0.2 / P0.4 still reserved ?
- can I work around this redundancy - and not have to reserve P0.2 nor P0.4 pins ?
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