PSoC™ 5, 3 & 1 Forum Discussions

PSoC®3 and PSoC®5 devices feature a Direct Memory Access (DMA) engine, which can used for data transfer between on-chip elements without any CPU intervention. The DMA engine is part of a high performance bus known as the peripheral hub (PHUB). The PHUB is a programmable and configurable central bus backbone within PSoC3/PSoC5 devices that ties the various on-chip system elements together. It consists of multiple spokes; each spoke is connected to one or more peripheral blocks.

The DMA with the help of Transaction Descriptors (TD) can move data from a source to destination at very high speeds. The TDs can be chained together to perform complex data transfers. The following diagram illustrates a simple data transfer using DMA.

The key features of PSoC® 3 and PSoC® 5 DMA are:

    
• 24 DMA channels
    
• Each channel has one or more Transaction Descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined
    
• TDs can be dynamically updated
    
• Eight levels of priority per channel
    
• Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction
    
• Each channel can generate up to two interrupts per transfer
    
• Transactions can be stalled or canceled
    
• Supports transaction size of infinite or 1 to 64k bytes
    
• TDs may be nested and/or chained for complex transactions
   

Please refer AN52705 - PSoC® 3 and PSoC 5 - Getting Started with DMA for information on different ways to configure the DMA channel and TD to perform data transfers. The application note also has example projects and a brief video.

Hello All,

Do PSoC 3/5 support hardware reconfiguration similar to PSoC 1? Can this be done during run time?

Thanks,

Alex

PSoC®3 and PSoC®5 devices feature a Direct Memory Access (DMA) engine, which can used for data transfer between on-chip elements without any CPU intervention. The DMA engine is part of a high performance bus known as the peripheral hub (PHUB). The PHUB is a programmable and configurable central bus backbone within PSoC3/PSoC5 devices that ties the various on-chip system elements together. It consists of multiple spokes; each spoke is connected to one or more peripheral blocks.

The DMA with the help of Transaction Descriptors (TD) can move data from a source to destination at very high speeds. The TDs can be chained together to perform complex data transfers. The following diagram illustrates a simple data transfer using DMA.

The key features of PSoC® 3 and PSoC® 5 DMA are:

    
• 24 DMA channels
    
• Each channel has one or more Transaction Descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined
    
• TDs can be dynamically updated
    
• Eight levels of priority per channel
    
• Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction
    
• Each channel can generate up to two interrupts per transfer
    
• Transactions can be stalled or canceled
    
• Supports transaction size of infinite or 1 to 64k bytes
    
• TDs may be nested and/or chained for complex transactions
   

Please refer AN52705 - PSoC® 3 and PSoC 5 - Getting Started with DMA for information on different ways to configure the DMA channel and TD to perform data transfers. The application note also has example projects and a brief video.

Cypress Semiconductor has completed the production programming qualification for Hilo Systems (http://www.hilosystems.com.tw/). The qualification covered all electrical requirements, algorithm support (SWD protocol only), and verification of device sockets. Cypress has qualified all 48-QFN, 48-SSOP, 68-QFN, and 100-TQFP sockets from Hilo Systems for programming PSoC3 devices.

Read more about this here, http://www.cypress.com/?rID=55804&cache=0

I am using CYACKIT-00 PSOC development kit... and to check whether UART is functioning or not i tried connecting arduino Rx-Tx directly to Tx-Rx of kit and even the ground are kept common still there is no communication between the two.. what could be the possible error... reply ASAP..thnks

I'm trying to implement a VME interface using a PSoC devices, but there are some things I would know.

    
• How a status and controll register are accessed from uC ?
  
    
• For example, If I use two 8bit status registers for reading a 16bit data bus, using the cortex-M3, the reading will be performed contemporarily or it needs two or more clock intervals?
  
    
• How they are mapped on PSoC?
  
    
• What type of internal bus they use?
  
    
• Could I associate the same variable at two or more status or controll registers?
  
    
• There is a way to choose to use the FIFO registers contained in the UDBs or it is the IDE that assign the internal resources?
   

Thanks in advance