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When we made Port 1 Hi Z Analog, we can no longer program the PSoC3 with our host chip, but can still program with the MiniProg3. Our host chip uses ...
When we made Port 1 Hi Z Analog, we can no longer program the PSoC3 with our host chip, but can still program with the MiniProg3. Our host chip uses active drive up/down when writing and driving XRES, and a pullup with receiving.
We found the problem - in PSoC Creator 4.3, when we set the pin to Hi Z Analog, it of course made the all of Port 1 Hi Z Analog. There was a side effect - in the Design Wide Resources > System section, it changed Programming\Debugging Debug Select to GPIO, which knocked out our ability to program from our host chip. We then changed it back to SWD, we could then program from our host chip.
On a side note, even while Programming\Debugging Debug Select was set to GPIO, the MiniProg3 could still program the chip - can you tell us how that can happen?
We have a few boards at remote locations with out MiniProgs, and we'd like to be able to recover those chips with the host processor only.
CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit is not recognized as an USB Device. It is not possible to establish a connection between PC and the BLE Pioneer...
CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit is not recognized as an USB Device. It is not possible to establish a connection between PC and the BLE Pioneer Kit for flashing the binary. It is also not possible to restore the on-board PSoC 5LP CY8C5868LTI-LP039 programmer firmware KitProg2.
I am currently working on a project that requires the logging of some events. This requires more capacity than that provided by the EEPROM s...
I am currently working on a project that requires the logging of some events. This requires more capacity than that provided by the EEPROM so I am now considering using the rest of the flash space available (256k in total).
My only concern with doing this is that I would need to know which is the last row that contains my code as I do not wish to overwrite any of this of course.
I have been looking around and do not seem to be able to find any information on this. Would anyone know how to tell which rows are safe to write?
My device also uses a Bootloader, which only leaves me with the space between the last application row and the first metadata row.
The PSoC® 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.