In my application, there is a control interrupt (isr_1) with a period of 200us. The total time spent in the interrupt is approximately 180us. The UART is running at 115200 and the fifo is set to >4 so it uses the UART RX interrupt and the sw ring buffer for storing the data. As soon as I make the UART RX interrupt priority higher (priority 0) than isr_1 (priority 1) the PSoC resets every few seconds with the reset reason being WDT. Do you know what might cause this?
When the UART interrupt is at a lower priority (priority 7) everything works fine and I read the received data in the main loop. I measured the time spent in the UART interrupt and it about 1us.
Show LessWe are using the UART with the HW fifo of 4, we find that when disabling interrupts for long time (not for 4 fifo long), we start to loss bytes sometimes (for our opinion the HW fifo not works OK).
Here is our interrupt handler that we used for testing:
CY_ISR(drvUART_A_RxISR)
{
uint8 dataByte, statusByte;
uint16 receivedData;
uAmaxrcv=0;
do{
receivedData = UART_A_GetByte();
dataA[k] = receivedData;
k = (k+1)%BLEN_TEST;
dataByte = (uint8)(receivedData & 0x00FFu);
statusByte = (uint8)((receivedData & 0xFF00u) >> 8u);
if((statusByte & UART_A_RX_STS_FIFO_NOTEMPTY) != 0u){
if((statusByte & (UART_A_RX_STS_BREAK | UART_A_RX_STS_PAR_ERROR |
UART_A_RX_STS_STOP_ERROR | UART_A_RX_STS_OVERRUN)) != 0u){
g_drvUART_driverStatus.uart_rxStatusErr[DRV_UART_MODULE_A]++;
}
else{
drvUART_fifoPushByte(DRV_UART_RX_FIFO_A, dataByte);
uAmaxrcv++;
}
}
}while((statusByte & UART_B_RX_STS_FIFO_NOTEMPTY) != 0u);
if (uAmaxrcv > uAprevmaxrcv){
uAprevmaxrcv=uAmaxrcv;
}
}
What we have seen that when we care disabling the interrupt for short time (not more than 1 byte in 4 bytes HW fifo) we are not loosing bytes, but when we are increasing the time of disale interrupt (global interrupt) we start to loose bytes even when 'uAprevmaxrcv' is 2.
Thanks for any help,
Dudi
Show Less
Hi,
I'm hoping to port my code to PSoC 5 via the CY8CKIT-059. My project uses the imported NVRAM component (CE204087.cydsn). Following the procedure outlined in "002-04087_CE204087_Interfacing_SPI_nvRAM_with_PSoC_3__PSoC_5LP.pdf", I get:
" No drivers on signal "CS", bit(s) "0". "
" Every signal bit must have exactly one driver (e.g., connected to one schematic input terminal or one instance output terminal). The given bits do not have any drivers. Add drivers for the indicated signal bits. "
I get two seemingly identical errors as above, concerning the "CS" bit and two more concerning the "HOLD" bit.
Then there are a couple of the error below and Fitter Abort.
" Error in customizer for component "CyControlReg_v1_70" : Loading : (Unable to locate and customize component 'CyControlReg_v1_70' used in schematic 'C:\Users\...\Cypress\PSoC5\CE204087\CE204087.cydsn\NVRAM_SPI\NVRAM_SPI.cysch'.). "
I bet somebody knows how to fix this!?
I'm running Creator 4.4 on Windows 10. I've followed the procedure a couple of different times and tried cleaning prior to building...
Thanks.
-Dave
Show LessHi,
I've been trying to make a hardware based boost converter using PSOC5 but it isn't working. I have attached a picture of my hardware configuration.
The PWM's period is 21.333us and the listed sampling rate of the ADC is 100000, giving the system about 10us of time for the system to complete the DMA and trigger the interrupt along with running a few lines of code. However using the debugger the interrupt runs either only once or not at all. I know it at least has been set up properly because it can be triggered.
I have attached the project below and am hoping someone might have insight as to why it is not repeatedly triggering.
Any help would be appreciated
Show LessAre there any compatibility issues using a UBS-C connector with a PSoC5?
Hi,
I need to convert the code example that you can find in PSOC 4 kit 037 to PSOC 5LP PN:CY8C5888LTI-LP097.
The code example his name is sensor BLDC motor PSOC 4.
link:CY8CKIT-037 PSoC 4 Motor Control Evaluation Kit (cypress.com)
PLS convert it and explain how you do it.
How can i change the factors of measurements ADC?
PLS explain the functionality of the design.
Thank you.
BR,
Ilan
Show LessI am using a timer to detect a reset signal of 500us and then give a presence (in an interrupt)(this is a 1-wire communication) , the problem i am facing is that when i given in some other commands after this reset signal at times i am not able to either detect the reset and give presence or the presence is given in between the commands. (I use psoc lp 5)
The timer config as:
trigger: at falling edge
capture: raising edge
interrupt on capture
CR: this is the control reg to reset the timer block inside the interrupt
both the control reg and timer block are connected to 4MHz clock
24bit, period of: 16777216
I don't know the mistake i am doing in this case. Here is my isr:
CY_ISR(isr_1_Handler)
{
Count =Timer_INIT_PERIOD-Timer_ReadCounter();
if(Count>480*4)
{
CyDelayUs(15);
TX_Write(0);
CyDelayUs(102);
TX_Write(1);
CyDelayUs(2);
}
else if(Count>65*4 && Count<75*4)
{
CyDelayUs(2);
TX_Write(0);
CyDelayUs(11);
TX_Write(1);
CyDelayUs(2);
}
CR_Write(1);
}
Note: I tried adding in a flag inside the interrupt and giving the presence outside checking the flag and in that case it missed the resets even when only resets where given without any commands.
I am attaching master code that i used to generate the resets and command and also the timer code (this timer code doesn't do anything other than giving a presence whenever a reset is detected)
Have been trying it out for a long time and am getting errors when i haves huge cycles as 500 times 6 errors, when u run these in two codes in two different psocs u can see the issue. Any help would be great !
Show LessHi there,
I need an PWM signal so that I can trigger specific action depending on the level of the PWM. So I set up the PWM with interrupts enabled for terminal count event and compare 1 event. I expected to get an interrupt when the compare value matches the counter and at the end when the counter reaches zero. But I get two interrupts simultaneously, or only microseconds apart.
I clock the PWM with 10 kHz and set the period to 12000 and the compare value to 9000. The compare type is greater. I get a PWM signal with 300ms high value and a period of 1200ms as expected. But not compare 1 interrupt after 300ms as expected.
What do I miss here?
Show LessHey all,
I've got a project in the works that uses 3 UARTs. I manage to fit in the 3 required, but I want to add a 4th for debugging purposes if possible. This should be no problem, as I appear to have adequate UDB resources for a half-duplex UART according to the UART component datasheet:
However when I try to build, I'm running out of UDBs during placement. Looks like running out of macrocells? I'm curious as to why this is? Something to do with how macrocells get allocated maybe?
I'm using PSoC Creator 4.3, the PSoC5LP part is a CY8C5667AXI-LP040. I've attached the report file to this post. DBG_UART is the component name for the half-duplex I am trying to add. I had to put it in a .zip because apparently I can't upload .rpt or .txt files.
Appreciate any thoughts,
Thanks!
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