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In my application, there is a control interrupt (isr_1) with a period of 200us. The total time spent in the interrupt is approximately 180us. The UART...
In my application, there is a control interrupt (isr_1) with a period of 200us. The total time spent in the interrupt is approximately 180us. The UART is running at 115200 and the fifo is set to >4 so it uses the UART RX interrupt and the sw ring buffer for storing the data. As soon as I make the UART RX interrupt priority higher (priority 0) than isr_1 (priority 1) the PSoC resets every few seconds with the reset reason being WDT. Do you know what might cause this?
When the UART interrupt is at a lower priority (priority 7) everything works fine and I read the received data in the main loop. I measured the time spent in the UART interrupt and it about 1us.
What we have seen that when we care disabling the interrupt for short time (not more than 1 byte in 4 bytes HW fifo) we are not loosing bytes, but when we are increasing the time of disale interrupt (global interrupt) we start to loose bytes even when 'uAprevmaxrcv' is 2. Thanks for any help,
I'm hoping to port my code to PSoC 5 via the CY8CKIT-059. My project uses the imported NVRAM component (CE204087.cydsn). Following the procedure o...
I'm hoping to port my code to PSoC 5 via the CY8CKIT-059. My project uses the imported NVRAM component (CE204087.cydsn). Following the procedure outlined in "002-04087_CE204087_Interfacing_SPI_nvRAM_with_PSoC_3__PSoC_5LP.pdf", I get:
" No drivers on signal "CS", bit(s) "0". "
" Every signal bit must have exactly one driver (e.g., connected to one schematic input terminal or one instance output terminal). The given bits do not have any drivers. Add drivers for the indicated signal bits. "
I get two seemingly identical errors as above, concerning the "CS" bit and two more concerning the "HOLD" bit.
Then there are a couple of the error below and Fitter Abort.
" Error in customizer for component "CyControlReg_v1_70" : Loading : (Unable to locate and customize component 'CyControlReg_v1_70' used in schematic 'C:\Users\...\Cypress\PSoC5\CE204087\CE204087.cydsn\NVRAM_SPI\NVRAM_SPI.cysch'.). "
I bet somebody knows how to fix this!?
I'm running Creator 4.4 on Windows 10. I've followed the procedure a couple of different times and tried cleaning prior to building...
I've been trying to make a hardware based boost converter using PSOC5 but it isn't working. I have attached a picture of my hardware configuration...
I've been trying to make a hardware based boost converter using PSOC5 but it isn't working. I have attached a picture of my hardware configuration.
The PWM's period is 21.333us and the listed sampling rate of the ADC is 100000, giving the system about 10us of time for the system to complete the DMA and trigger the interrupt along with running a few lines of code. However using the debugger the interrupt runs either only once or not at all. I know it at least has been set up properly because it can be triggered.
I have attached the project below and am hoping someone might have insight as to why it is not repeatedly triggering.
I am using a timer to detect a reset signal of 500us and then give a presence (in an interrupt)(this is a 1-wire communication) , the problem i am fac...
I am using a timer to detect a reset signal of 500us and then give a presence (in an interrupt)(this is a 1-wire communication) , the problem i am facing is that when i given in some other commands after this reset signal at times i am not able to either detect the reset and give presence or the presence is given in between the commands. (I use psoc lp 5)
The timer config as:
trigger: at falling edge
capture: raising edge
interrupt on capture
CR: this is the control reg to reset the timer block inside the interrupt
both the control reg and timer block are connected to 4MHz clock
24bit, period of: 16777216
I don't know the mistake i am doing in this case. Here is my isr:
Note: I tried adding in a flag inside the interrupt and giving the presence outside checking the flag and in that case it missed the resets even when only resets where given without any commands.
I am attaching master code that i used to generate the resets and command and also the timer code (this timer code doesn't do anything other than giving a presence whenever a reset is detected)
Have been trying it out for a long time and am getting errors when i haves huge cycles as 500 times 6 errors, when u run these in two codes in two different psocs u can see the issue. Any help would be great !
I need an PWM signal so that I can trigger specific action depending on the level of the PWM. So I set up the PWM with interrupts enabled fo...
I need an PWM signal so that I can trigger specific action depending on the level of the PWM. So I set up the PWM with interrupts enabled for terminal count event and compare 1 event. I expected to get an interrupt when the compare value matches the counter and at the end when the counter reaches zero. But I get two interrupts simultaneously, or only microseconds apart.
I clock the PWM with 10 kHz and set the period to 12000 and the compare value to 9000. The compare type is greater. I get a PWM signal with 300ms high value and a period of 1200ms as expected. But not compare 1 interrupt after 300ms as expected.
I've got a project in the works that uses 3 UARTs. I manage to fit in the 3 required, but I want to add a 4th for debugging purposes if poss...
I've got a project in the works that uses 3 UARTs. I manage to fit in the 3 required, but I want to add a 4th for debugging purposes if possible. This should be no problem, as I appear to have adequate UDB resources for a half-duplex UART according to the UART component datasheet:
However when I try to build, I'm running out of UDBs during placement. Looks like running out of macrocells? I'm curious as to why this is? Something to do with how macrocells get allocated maybe?
I'm using PSoC Creator 4.3, the PSoC5LP part is a CY8C5667AXI-LP040. I've attached the report file to this post. DBG_UART is the component name for the half-duplex I am trying to add. I had to put it in a .zip because apparently I can't upload .rpt or .txt files.
I've only played with PSoC till now, but at last, I have got a real application, and I'm not sure of the best way to proceed. I am trying to read ...
I've only played with PSoC till now, but at last, I have got a real application, and I'm not sure of the best way to proceed. I am trying to read several 'Chinese scale' as used in verniers etc, as well as other format sensors.
Examples can be found on the web at Yuriys toys, Shumatec etc. I would like a solution that could be configurable. They all have a lot in common.
They are all 24-bit data(or multiples of) with a clock and data on positive or negative edge triggering
There is a gap between data packets that is orders of magnitude greater than the clock to distinguish start.
So it looks like all I need is a timer with the clock on reset to clear it if started near a new packet. The output of the timer then enabling a 24-bit shift register.
The problem is I'm struggling to figure out how to configure the shift register. I would have thought that at the terminal count (24 ) there would be an interrupt/DMA transfer to save the parallel data to memory. The shift out interrupt is ( I think) generated on the NEXT pulse, which of course I don't get as it's the first bit of the next data block. I looked at using the Timer block to create an SS signal for an SPI, but that's only 16 bit, so no good. I could use a 24 bit counter, but that seems overly complicated. Could anyone point me in the right direction, please? If that involves verilog I will have a problem as I need a proof of concept asap and I have Zero experience with Verilog.
The PSoC® 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.