Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob

PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
PSoC™ 5, 3 & 1
 Seems like there is a problem with using API ShiftReg_WriteRegValue(); and problem is being discussed with experts..    Instead of above function Shi... Show More
Anonymous
PSoC™ 5, 3 & 1
 Going from ES2 to ES3 silicon apparently requires the EEPROM_Start() which calls CyEEPROM_Start() that turns on EEPROM power.    ES2 did not require ... Show More
Anonymous
PSoC™ 5, 3 & 1
 Hi,    When i tried to program a project in my new PSoC 5 development kit (CY8CKIT-050), it asks for Select debug target.. and in my psoc creator it ... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi    How do i implement parallel to serial conversion and vice versa using the PSoC. Looks like i need extra hardware. Is that so?         Regards   ... Show More
Anonymous
PSoC™ 5, 3 & 1
 http://www.cypress.com/?docID=19093    precis and to the point. Show More
Anonymous
PSoC™ 5, 3 & 1
 Hello friends    Cypress Developer Community is providing an opportunity for all its forum members to come up with a new innovative component. These ... Show More
Anonymous
PSoC™ 5, 3 & 1
I have a CY3290-TMA300 DVK, yesterday I used psoc programmer to upgrade it's firmware but failed, and then I could not find the port in psoc programme... Show More
Anonymous
PSoC™ 5, 3 & 1
I'm trying to use CYFINSP with Cy8c20446a. The CYFISNP_Start doesn't work. Are there some special setups that has to be done with this device ? The ra... Show More
Anonymous
PSoC™ 5, 3 & 1
 Project: ADC => DMA => Filter => DMA => DAC    The input is provided as a DTMF waveform signal. The amplitude is in range 0.2 ..2.2 V.    The problem... Show More
Anonymous
PSoC™ 5, 3 & 1
 Hello All    I am using CRC component . The polynomial selected is x16+x15+x2+1. I am feeding the data serially via shift register.    When the data ... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.