PSoC™ 5, 3 & 1 Forum Discussions

Issue/Problem:

I am using hardware UART (RX8 or TX8 UM) with CapSense CSD/SmartSense/CSDADC UM in CY8C21x34 family of PSoC 1 devices. My UART is not working properly.

Cause:

Most probable cause is the clock input of RX8/TX8 UM. If the clock input is any of the VC1, VC2 or VC3 dividers, then the intended baud rate obtained from those clock sources for the UART will be destroyed during program execution. The reason being based on Resolution and Scanning speed CSD/CSDADC/SmartSense UM modifies VC1, VC2 and VC3 dividers. The information and details on how they impact can be found in the UM datasheet (below figure).

So if you set the input clock of RX8 as VC2 and fix a baud rate of 150 ksps (SysClk = 24MHz, VC1 = Sysclk/16; VC2 = VC1/10). With a CSD resolution of 12 bit and normal scan speed, your baud rate changes to 750 ksps (Sysclk = 24, VC1 = Sysclk/4, VC2 = VC1/8). And this happens when CSD_Start() API is called. Worser would be using SmartSense, where the values of these dividers are not exposed to user and they change with each sensor.

Solution/Possible workarounds:

    
1. Use external Clock option (ROW_INPUT_x lines) for the input clock and route the clock to a pin.
    
2. If using CSD/CSDADC, then based on the resolution and scan speed selected for the design calculate the baud rate in CY8C21x34 and tune the other end UART RX/TX to the baud rate obtained.
   

This bug is not confined to UART, it is valid for all the sources from digital block to interrupts like VC3 ISR which uses these system clock dividers. UART was taken as an example as it is the most common issue faced by customers trying to communicate the CSD button status over UART lines.

Please feel free to add your thoughts on other possible workarounds too.

  Hi people,

Cypress(PSoC 3/5) is Planning to start a Component Design Contest.

The purpose of this Design Contest is to make the Community users get more acquainted with designing components in PSoC 3/5. Once we start designing components, we will be able to understand the architecture of the PSoC UDBs better and realise how flexible PSoC 3/5 really are!!!

Contest Rules : A Complete specification for the component will be given every friday.

You get 1 week to design it, your deadline for submission will be the next friday.  Timeline of submission plays a major role in deciding who the winner is !. The quality of the design matters ofcourse.

The winner will be decided by a bunch of engineers at cypress and he shall be awarded with 200CDC points.

Every Individual on planet Earth shall participate.

The First specification will be posted this friday (7th of december). We will initially start with simple designs and move complex over the weeks.

Get ready for a healthy challenge. Though there is only one winner, every one gets benefited by the learnings from it.

On the course of the design, you shall post all queries and it shall all be clarified.

Regards,

Ramnath R K

Set 4 of updated KB's for PSoC5 LP

http://www.cypress.com/?id=4&rID=52243

http://www.cypress.com/?id=4&rID=44324

http://www.cypress.com/?id=4&rID=38575

Hello All,

I am using psoc as slave with i2c read buffer of size 8 byte. Master polls psoc in every 100ms.

Very frequently on i2c analyzer i am getting all 8 byte with 0xFF data with i2c Control/Status register I2CHW_RD_ OVERFLOW bit set.

As per my understanding this may cause because of either

1. doing capsesense scan in mainloop() .

2. enabling disabling global interrupt in mainloop().

have anyone faced similar problem before?

Thanks in advance.