PSoC™ 5, 3 & 1 Forum Discussions
Hello,
we are beginners in the PSOC5 programming. We tried to build a system with some communication interfaces (USB, UART, SPIO, I2C) but it seemed that the PSOC5 is too small. We cant locate the error in the report file.
We used "PSoC Creator 2.2 Component Pack 5 (2.2.0.293)".
The device was "CY8C5868AXI-LP032".
Thank you for the help
---------------------------------------------------------------------------------------
.....
Analog Placement ...
Log: apr.M0058: The analog placement iterative improvement is 26% done. (App=cydsfit)
Log: apr.M0058: The analog placement iterative improvement is 55% done. (App=cydsfit)
Analog Routing ...
Analog Code Generation ...
Digital Placement ...
Error: plm.M0046: E2071: The design requires 25 UDB(s) but the device has 24. See the report file for details.
Error: plm.M0046: E2055: An error occurred during placement of the design.
Error: plm.M0046: "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin/sjplacer.exe" failed (0x0000000B)
Dependency Generation ...
Clean Temporary Files ...
Error: cdf.M0005: CyDsFit aborted due to errors, please address all errors and rerun CyDsFit. (App=cydsfit)
--------------- Rebuild Failed: 03/23/2013 17:21:33 ---------------
------------ our results in test04.rpt
Resource Type : Used : Free : Max : % Used
============================================================
Digital domain clock dividers : 7 : 1 : 8 : 87.50%
Analog domain clock dividers : 1 : 3 : 4 : 25.00%
Pins : 64 : 8 : 72 : 88.89%
UDB Macrocells : 153 : 39 : 192 : 79.69%
UDB Unique Pterms : 321 : 63 : 384 : 83.59%
UDB Total Pterms : 358 : : :
UDB Datapath Cells : 21 : 3 : 24 : 87.50%
UDB Status Cells : 19 : 5 : 24 : 79.17%
Status Registers : 3
StatusI Registers : 14
Sync Cells : 8 (in 2 status cells)
UDB Control Cells : 17 : 7 : 24 : 70.83%
Control Registers : 12
Count7 Cells : 5
DMA Channels : 0 : 24 : 24 : 0.00%
Interrupts : 10 : 22 : 32 : 31.25%
DSM Fixed Blocks : 1 : 0 : 1 : 100.00%
VIDAC Fixed Blocks : 0 : 4 : 4 : 0.00%
SC Fixed Blocks : 0 : 4 : 4 : 0.00%
Comparator Fixed Blocks : 0 : 4 : 4 : 0.00%
Opamp Fixed Blocks : 0 : 4 : 4 : 0.00%
CapSense Buffers : 0 : 2 : 2 : 0.00%
Decimator Fixed Blocks : 1 : 0 : 1 : 100.00%
I2C Fixed Blocks : 1 : 0 : 1 : 100.00%
Timer Fixed Blocks : 4 : 0 : 4 : 100.00%
DFB Fixed Blocks : 0 : 1 : 1 : 0.00%
USB Fixed Blocks : 1 : 0 : 1 : 100.00%
LCD Fixed Blocks : 0 : 1 : 1 : 0.00%
EMIF Fixed Blocks : 0 : 1 : 1 : 0.00%
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
SAR Fixed Blocks : 0 : 2 : 2 : 0.00%
there is a problem in programming kit-001 , non of the module is getting programmed. i have checked all its jumper setting and project setting but still i m not able to prgrame it. Can anyone help me with it. please help me as soon as possible since i have to subbmit my project after 10 days. please reply me soon
Show Lessthere is a problem in programming of kit CY8CKIT-001 using miniprog3 in creator as well as designer.
error message is: can not accquire the device
if anybody know about this problem ,please help me
thank you
Show LessTRM explains about Grant Allocation fairness Algorithm, but the description is not sufficient is what I feel.
Here is a little more explaination of this algorithm.
"In this method, the channel 0 and 1 take highest priority and no other prior-ity can interrupt the channels with priority 0 and 1.A DMA Channel of priority 0 and priority 1 occupy the bus 100%. Rest of the priorities share the bus based on the number of channels requested at that time. Because pri-ority 0 has higher priority than 1, priority 0 can interrupt priority 1.
In both the cases, a DMA channel of low priority can be interrupted by a high priority channel only during the source engine phase.
Under ideal conditions the Arbitration phase takes one cycle.
The channels with priorities 2-7 are given the access according to Table
Priority Level Bus Allocation Percentage
2 50
3 25
4 12.5
5 6.3
6 3.1
7 1.5
When DMA channels of varied priority request for DMAC at a time, 100% of bus bandwidth will be allocated for channels of priority 0 or 1. Table applies only if DMA channels with priorities 2-7 are requesting simultaneously. Otherwise, the DMA channel with higher priority is given more access than Table shows.Attached file shows a channel priority wheel that describes how the next 63 requests are handled if all channels with priorities 2 to 7 are requesting simultaneously"
If a channel with priority 2 to 7 is NOT requesting, the slots of the missing channel priority are used by the channel with the highest priority. In that case, channels with higher priority get more access than channel priority wheel shows."
TRM explains about Grant Allocation fairness Algorithm, but the description is not sufficient is what I feel.
Here is a little more explaination of this algorithm.
"In this method, the channel 0 and 1 take highest priority and no other prior-ity can interrupt the channels with priority 0 and 1.A DMA Channel of priority 0 and priority 1 occupy the bus 100%. Rest of the priorities share the bus based on the number of channels requested at that time. Because pri-ority 0 has higher priority than 1, priority 0 can interrupt priority 1.
In both the cases, a DMA channel of low priority can be interrupted by a high priority channel only during the source engine phase.
Under ideal conditions the Arbitration phase takes one cycle.
The channels with priorities 2-7 are given the access according to Table
Priority Level Bus Allocation Percentage
2 50
3 25
4 12.5
5 6.3
6 3.1
7 1.5
When DMA channels of varied priority request for DMAC at a time, 100% of bus bandwidth will be allocated for channels of priority 0 or 1. Table applies only if DMA channels with priorities 2-7 are requesting simultaneously. Otherwise, the DMA channel with higher priority is given more access than Table shows.Attached file shows a channel priority wheel that describes how the next 63 requests are handled if all channels with priorities 2 to 7 are requesting simultaneously"
If a channel with priority 2 to 7 is NOT requesting, the slots of the missing channel priority are used by the channel with the highest priority. In that case, channels with higher priority get more access than channel priority wheel shows."
Show Lessi am new to PSoc. i have PSoc3(CY8C3245) controller.i have PSoc designer version 5.2 installed .but i not found my device in device list while creating new project.so what should i do now????????
Show LessHI Forum,
I'd like to know how to know the value of a variable after certain executions have elapsed. I tried "Add Watch" in the watch window under debugger - but the value of the variable remains as 0x0000 inspite of numerous Compile-Run iterations.
I'm sure that the increment occurs as I also toggle a LED inside the same block which I confirm using a DSO.
Awaiting replies,
RAM
Show LessI guess many(myself included) wouldve noticed the references to a mythical(or not?) PSoC 4 part throughout Creator 2.0.
If someone could share more on the myth,whats that about?
Show LessHow do I convert the hex to a decimal base 0 to 9.
void Display_Result(void)
{
LCD_Char_Position(0,6);
LCD_Char_PrintInt8(HYT221_Read_Buff[0] & 0x3f); //Mask HYT humidity the highest two status bits
LCD_Char_PrintInt8(HYT221_Read_Buff[1]);
LCD_Char_PrintNumber(unit8,HYT221_Read_Buff);
temp = astio(temp, HYT221_Read_Buff[1], 16);
LCD_Char_PrintString(" ");
LCD_Char_Position(1,6);
LCD_Char_PrintInt8(HYT221_Read_Buff[2]);
LCD_Char_PrintInt8(HYT221_Read_Buff[3] & 0xfc); //Mask HYT temperature the lowest two status bits
LCD_Char_PrintString(" ");
}
Dear Sir/madam
Application Note - AN76530
Heading - PSoC® 1 Automotive Ultrasonic Distance Measurement
In the above mentioned application note, on page no - 13, there is a connection for the Power Jack .
I just wanted to know that what Input unregulated voltage would be given to this power jack.
and wether it would be DC or Ac .
Waiting for your solution regarding the same
Regards
Show Less