PSoC™ 5, 3 & 1 Forum Discussions

Hi, I am new to PSoC programming, and I have encountered some confusing
behavior. I have a PSoC5 LP device, and I'm trying to develop a parallel
interface using a port on the device. I began testing my write speed by simply
writing two alternating values on the port: specifically, I wrote 0x40 and 0x01
to the correct register for P6. These values will alternate driving P6_6 high
and P6_0 high. That is, while P6_6 is high, P6_0 is low, and vice versa. If I do
this at a rather slow speed, I get a nice waveform that you'd expect from these
pins, What is strange is that whenever I try to optimize the bus speed and clock
speed to achieve an overall frequency somewhere above ~2MHz, I get a somewhat
deformed duty cycle on both pins. So where before I'd have about a 50% duty
cycle on both pins, now I have about a 33% duty cycle on one pin, and a 66% duty
cycle on the other. Here are some images of the waveforms at the slow and high
speeds, respectively:

 Hi,

Attached code demonstrates how to take the recived data inside UART ISR. Following steps needs to be performed on PD 5.3 for the same.

1. Create a custom UART user module. For that select Tools->User Module Customization Wizard. Select the User module and press Copy. Once the custom user module is created open the template of UARTINT.asm file from the folder where the module is stored.

2. Paste the following marker area just before the reti instruction that is present in the end of UARTINT.asm template file.

;@PSoC_UserCode_BODY_3@ (Do not change this line.)

   ;---------------------------------------------------

   ; Insert your custom assembly code below this banner

   ;---------------------------------------------------

   ;   NOTE: interrupt service routines must preserve

   ;   the values of the A and X CPU registers.

   ;---------------------------------------------------

   ; Insert your custom assembly code above this banner

   ;---------------------------------------------------

   ;---------------------------------------------------

   ; Insert a lcall to a C function below this banner

   ; and un-comment the lines between these banners

   ;---------------------------------------------------

   ;PRESERVE_CPU_CONTEXT

   ;lcall _My_C_Function

   ;RESTORE_CPU_CONTEXT

   ;---------------------------------------------------

   ; Insert a lcall to a C function above this banner

   ; and un-comment the lines between these banners

   ;---------------------------------------------------

   ;@PSoC_UserCode_END@ (Do not change this line.)

3. Place the custom user module,Build the project and open UARTINT.asm file.

4. Uncomment the lines 

   PRESERVE_CPU_CONTEXT

   lcall _My_C_Function

   RESTORE_CPU_CONTEXT

5. Define the function My_C_Function in the main.c and read the received data inside the function.

Please find attached project for your convenience. Thank you. 

Regards,

Keerthy

 Hi,

As part of our firmware upgrade (previosuly used external SPI Flash), I am using the upper two arrays (2,3) of a PSOC 5LP to store a new firmware image. 

All of the executable code lives in Array0. Here is my problem. It seems as though the CPU stalls during the entire time it takes to write the flash. In the TRM, it seems to indicate that the cache controller and SPC can access different banks (arrays) without conflict. However, if they are in the same bank, the cache controller must wait for the SPC operation to complete.

In my case, there should be no conflict ??? Any ideas ? This causes the rest of the system functionality to fail while the writes finish....

Is there something I am mis-interpreting ?

Thanks in advance

The code is quite simple.

I previously set the ECC buffer and called the settemp functions. The values get written fine.

static uint32 FlashPage256ProgramReadModifyWrite(unsigned long offset, uint8 *buf, uint16 len){    uint8 array=2;     uint8 row=0;     uint8 byteOffset;     uint32 origOffset = offset;     cystatus status;     if (offset > FLASH_MAX_OFFSET)     {        return 2;     }    if (len > FLASH_ROW_SIZE)     {        return 3;     }    if (offset > 0x0000FFFF)     {        ++array;  // 4th array        offset -= 0x00010000; // adjust offset to account for new array    }    row = offset / FLASH_ROW_SIZE;      // now figure out overwrite data    byteOffset = offset - (row * FLASH_ROW_SIZE);     FlashRead(origOffset & 0xffffff00, flashTempBuf, FLASH_ROW_SIZE);     memcpy((flashTempBuf +  byteOffset), buf, len);      status = CyWriteRowData(array, row, flashTempBuf);     if (CYRET_SUCCESS != status)     {        return 5;     }    if (memcmp((void *)((origOffset & 0xffffff00) + FLASH_DOWNLOAD_BASE_OFFSET), flashTempBuf, FLASH_ROW_SIZE) != 0)     {        return 6;     }     return 0;}

Dear All,

I couldn't find any timing information (number of clock cycles) for a single byte DMA transfer. How many clock cycles are needed between drq and nrq whwn one byte is transferred from ADC output register to control register?

BR,

   Esa

 I've a project with I2C (slave and fixed function) and an ADC_SAR_Seq with many differential inputs (about 20).

ADC works perfect without cpu work (only to get values after a complete conversión of the 20 inputs).

But I2C doesn't work, the master says BUSY. After a while of testing and retesting I've tested omit ADC_SAR_Seq_StartConvert(); and voilá, I2C works perfect.

First I thought about high SPS, so down it. but no improvement, only omiting StartConvert solves the I2C problem.

Also commenting code into ADC ISR solves the problem and I2C begin to work. 

The code for the I2C is simple and it's into the for loop:

if(0u != (I2C_SlaveStatus() & I2C_SSTAT_WR_CMPLT))

{

/* Read the number of bytes transferred */

byteCnt = I2C_SlaveGetWriteBufSize();

/* Clear the write status bits*/

I2C_SlaveClearWriteStatus();

/* Move the data written by the master to the read buffer so that the master can read back the data */

for(indexCntr = 0; indexCntr < byteCnt; indexCntr++)

{

rdBuf [indexCntr] = wrBuf[indexCntr]; /* Loop back the data to the read buffer */

}

/* Clear the write buffer pointer so that the next write operation will start from index 0 */

I2C_SlaveClearWriteBuf();

/* Clear the read buffer pointer so that the next read operations starts from index 0 */

I2C_SlaveClearReadBuf();

}

/* If the master has read the data , reset the read buffer pointer to 0 and clear the read status */

if(0u != (I2C_SlaveStatus() & I2C_SSTAT_RD_CMPLT))

{

/* Clear the read buffer pointer so that the next read operations starts from index 0 */

I2C_SlaveClearReadBuf();

/* Clear the read status bits */

I2C_SlaveClearReadStatus();

}

Again the code into the isr is simple:

CY_ISR( ADC_SAR_Seq_ISR )

{

int i;

  for( i=0;i<20;i++)

{

ichannels = ADC_SAR_Seq_GetResult16(i);

}

}

Best regards.

DEVICE: CY8C5868AXI-LP035

I am using PSoC Creator 3.0 for my design and I was interested in SAR ADC component. In the example project of ADC_SAR_Seq there is a project in which four on-board (evaluation kit) VDACs give input to 4-channel SAR ADC and example projects helps to demonstrate that ADC can properly convert those voltages. I have mainly two problems with this:

1) I am using evaluation board. The Initial VDAC settings are 200 mV, 400 mV, 600 mV and 800 mV. The voltages, although, that are getting displayed on the LCD are 300, 600, 900 and 1200 mV respectively (readings of C1, C2, C3, C4). When I tried changing the VDAC settings to 300, 600, 900 and 1200, the voltages getting displayed on the screen are 450, 900, 1050 and 1800.

So is there a scaling factor of 1.5 somewhere which I am missing? The example project, I suppose should not behave like this, because I haven't made any kind of alterations inside the project.

2) When I faced above problem, I tried to replicate the exact project (with same pin numbers and configuration). I copied the exact same code from the project. When I tried to build it, it spewed out some errors that

a) Analog teminal "vdac_ref" on ADC_SAR_SEQ_v1_10 is unconnected (even though I have internally bypassed vdac_ref)

b) Analog terminal "AMuxHw_1.BoutTerm" on ADC_SAR_SEQ_v1_10 is unconnected.

Can someone please explain what is happening here? 

Hello

We are developing one application which requires to use bootloader component given by Cypress.

But for some reason we are facing Memory issues so we decided to create our own bootloader.

Can you please provide some inputs for creating our own bootloader using Cypress Creator IDE or to do some changes in existing bootloader  component.